Confirming BIST Sequence

Question

I am trying to use AD9269's Built-In Self-Test (BIST) function and have a couple of questions. 
 For some context, I have created a program to do this based on information on page 26 of the AD9269's datasheet. Currently, my programming sequence is as follows: 
 
 Perform a reset by writing 0x3C to the SPI port configuration register (0x00). 
 Write 0x0E to the BIST enable register (0x0E). 
 Write 0x01 to the Transfer register (0xFF). 
 Wait until Bit 0 of the MSIR LSB register to clear. 
 If B it 0 of the MSIR LSB register is cleared, then the BIST is completed and performed correctly. 
 
 My questions are: 
 
 I am using AD9269-20 with a 20 MHz clock. Does that mean the BIST operation runs for 25.6 &mu;s (512&times;50 ns)? 
 Is the sequence above correct? Did I miss something? 
 From my tests, when the BIST enable register is observed after being set, Bit 3 doesn't get cleared automatically like Bit 0, is this the suppose to happen? Should I clear Bit 3 manually? 
 On the sequence above, I didn't do any write to the Test mode register (0x0D) to select PN 9 or PN 23 sequence. I left the register value to its default value (0x00). Should I select PN 9 or PN 23 sequence before running the BIST?

JAlipio · Accepted Answer

Hi nics17 
 Thank you for using AD9269. 
 
 Yes, with a 20 MHz clock, the BIST operation should run for 25.6 &mu;s. This is calculated as 512 clock cycles &times; 50 ns (the period of a 20 MHz clock) = 25.6 &mu;s. 
 Your sequence looks mostly correct. However, you should also configure the Test Mode register 0x0D to select either the PN9 or PN23 sequence before enabling the BIST. This ensures the correct test pattern is used. 
 Bit 2 not clearing automatically is expected behavior. According to the datasheet, Bit 2 indicates the BIST mode is enabled, and it does not clear automatically. You should manually clear Bit 2 after the BIST operation is complete. 
 Yes, you should select either the PN9 or PN23 sequence in the Test Mode register 0x0D before running the BIST. 
 
 Here&rsquo;s an updated sequence incorporating these points: 
 
 Perform a reset by writing 0x3C to the SPI port configuration register 0x00. 
 Write 0x06 (for PN9) or 0x05 (for PN23) to the Test Mode register 0x0D. 
 Write 0x05 to the BIST enable register 0x0E. 
 Write 0x01 to the Transfer register 0xFF. 
 Wait until Bit 0 of the MSIR LSB register 0x24 clears. 
 If Bit 0 of the MSIR LSB register 0x24 is cleared, then the BIST is completed and performed correctly. 
 Manually clear Bit 2 of the BIST enable register 0x0E. 
 
 Reference: AD9269 (Rev. B))

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Confirming BIST Sequence