Hi,
We are AD9681 ADC in our design for DAQ voltage and current measurement purposes. It is interfaced with Ultrascale FPGA. We are running the ADC at 50 Msps speed.
Here are the questions:
1. What is the maximum PCB trace length should be allowed on the data lane and DCO clock between the ADC and FPGA? It is not mentioned in the Application note / Datasheet. Is there any absolute max length limit on the trace length?
2. Currently, our board has a 240 mm trace running between ADC and FPGA on data and clock traces. Its length is matched within 1mm. Is there any potential impact on 240 mm ?
3. Are there any settings that will help if the trace length is higher? or driver strength?