AD9681 ADC Length Matching between the DCO and data lanes - Knobs to tweak

Related thread: LVDS Data and clock maximum length on PCB - Q&A - High-Speed ADCs - EngineerZone

Here questions are different. 

If the distance between the DCO and data lanes is higher or at 40 mm. What methods will help to avoid data misalignment on that bank?

Maximum length I will take from above thread. But knobs to tweak the skew between the DCO and data.

Hi GovindAlagan 

There is an output phase adjusts on the register 0x16 of the AD9681, but it seems that it is applied to both DCO1 and DCO2, so they can’t be set to different values. In that case, you'll have to do a phase adjustment on the FPGA side. Kindly give us some time to verify this and get back to you.

Yes. that helps. If we get the phase adjustment for the 40 mm difference, it will be helpful, or a method to calculate also helps. 

Hi GovindAlagan 

You can adjust the output clock phase DCO1 & DCO2 separately by selecting the one of the Chip Select Bar (CSB) an active low control that gates the read and write cycles. CSB1 enables/disables the SPI for Bank 1; CSB2 enables/disables the SPI for Bank 2.

However, it is still recommended to tie CSB1 and CSB2 together and be controlled with the same signal.