Recommended Oscillator for high speed ADC

Hi mohammadsdtmnd 

mohammadsdtmnd said:

LTC2241 or LTC2253 both have evalution board, but it does not have recommendations for its Oscillator clock signal. I wonder EV board recommended balun transformer but not oscillator such important part! Am I right? Please provide recommended part by classification of size price and actuall effect of low price oscillators on sam

For high-speed ADCs, oscillators like the Crystek CVHD-950 Series or Abracon ASVTX-09 Series are recommended due to their low phase noise and jitter characteristics. Using low-cost oscillators can introduce higher jitter, which affects the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) of the ADC. This can degrade the overall performance, especially in high-speed applications.

mohammadsdtmnd said:

I have seen in some EV usage of NC7SZ04P5X inverter buffer sometimes with NL17SZ74 flip-flop in 2MSPS ADC. I've heared they can reduce jitter. But how and how much? Why not use one of them only? Is it possible to use them for high speed ADC's too 100-200MSPS?

Using both an inverter buffer and a flip-flop can provide better jitter performance than using either alone. The inverter buffer sharpens the clock signal transition which reduce phase noise, while the flip-flop ensures synchronization and reduce timing errors, resulting in a cleaner and stable clock signal with reduced jitter.

Hi mohammadsdtmnd 

mohammadsdtmnd said:

LTC2241 or LTC2253 both have evalution board, but it does not have recommendations for its Oscillator clock signal. I wonder EV board recommended balun transformer but not oscillator such important part! Am I right? Please provide recommended part by classification of size price and actuall effect of low price oscillators on sam

For high-speed ADCs, oscillators like the Crystek CVHD-950 Series or Abracon ASVTX-09 Series are recommended due to their low phase noise and jitter characteristics. Using low-cost oscillators can introduce higher jitter, which affects the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) of the ADC. This can degrade the overall performance, especially in high-speed applications.

mohammadsdtmnd said:

I have seen in some EV usage of NC7SZ04P5X inverter buffer sometimes with NL17SZ74 flip-flop in 2MSPS ADC. I've heared they can reduce jitter. But how and how much? Why not use one of them only? Is it possible to use them for high speed ADC's too 100-200MSPS?

Using both an inverter buffer and a flip-flop can provide better jitter performance than using either alone. The inverter buffer sharpens the clock signal transition which reduce phase noise, while the flip-flop ensures synchronization and reduce timing errors, resulting in a cleaner and stable clock signal with reduced jitter.

Hi  JAlipio  thanks

How flip-flops ensure synchronization and what that means?jitter? How? Will this make them to grade of cvhd or asvtx?

Hello,

For high-speed converters like the LTC converters in your email, one may want to consider low phase noise/jitter CLK oscillators with LVPECL outputs like those available from skyworks.

570ACB000738DG Skyworks Solutions Inc. | Crystals, Oscillators, Resonators | DigiKey

What uo mean from flip flops ensures synchronization since LT2323 tells: If jitter from the FPGA is not a concern, the flip-flop can be eliminated and replaced with an inverter such as the NC7SZ04P5X. Then how it neglect FPGA jitter effect?

Hello,

The jitter of a flip-flop used for resynchronization will only be good as the "clean" clock that will be used for resynchronization.  That said............one needs to start with a clean clock source to begin with that is derived directly via a stand-alone oscillator or alternatively a high performance PLL circuit that features a low phase noise VCO.  Note that cost of PLL/VCO solution is dominated by the low phase noise characteristics of the external or internal VCO.  The ADF4372 can provide 33 fsec rms jitter with two differential CML outputs.

ADF4372 (Rev. A)

A clock distribution IC like the HMC7044 (with on-chip VCO having jitter of 44 fsec rms at 2.45 GHz) or HMC7043 (no PLL/VCO) can also be considered if clock generation and synchronization is required for other IC's on the PCB.

HMC7044 (Rev.E)

Hi PMH2023 
I'm not sure have you read the quote from LTC2323, I've just asked for the role of flip flop, Don't understand what you want to tell? You want to say: using PLL and syntheser can help reduce jitter of clock source, am I right? That is interresting to me. But I'm now asked: LTC2323 told: you can neglect flip flop (NL17sZ4USG) if you are not concerned about FPGA jitter here:

I asked flip flop exactly how reduce/neglect jitter of FPGA?

Hello,

Clock jitter will degrade the SNR performance of the ADC based on the max input frequency of the waveform that the ADC will sample along with the level of the input signal relative to the ADC's full-scale level.  Plot below shows how SNR of an ADC will degrade for a full-scale sinewave (i.e. 0 dBFS) for different rms jitter values.  The system designer will need to determine what is an acceptable level of jitter to meet their performance targets.


The circuit below shows how a D flip flop can be configured to clean up a poor jitter clock source which is "retimed" by the "clean" clock source applied to CP.   The earlier advice provided ideas on how this "clean" source could be provided as well as how one can use a clock generation circuit to provide synchronous clocks to both the ADC and FPGA thus avoiding any need for a retiming D flip-flop solution.