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Reducing sampling speed

Thread Summary

The user inquires about using the AD9699 ADC at 2 GSPS, despite the minimum rated sampling rate of 2.5 GSPS. The support engineer confirms that while the ADC can function at lower rates, performance will degrade. The SNR degradation at 2 GSPS is expected to be around 1 dB over 700 MHz, which might still be acceptable for the user's application. The AD9689, a dual-channel ADC, is suggested as an alternative but is more expensive.
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Category: Datasheet/Specs
Product Number: AD9699

Hi,

We want to use this component to sample at 2 GSPS, and while we understand that most users want the highest sampling rate, 2 GSPS full bandwith sampling fits perfectly our requirement.  Unfortunately in Table 4 "SWITCHING SPECIFICATION" no minimal clock Rate is provided, but the minimal sampling rate is given at 2500MHz. So does this make sense, is really not possible to underclock the converter?

Later in "clock input consideration" the differential input is qualified between 100MHz and 6 GHz, no minimum is provided

Best regards

  • Hi  

    Thanks for your interest in AD9699.

    Unfortunately, this ADC minimum sampling rate is only rated for 2.5 GSPS.

    Although, it can still function at lower sampling rate (< 2.5 GSPS) but its performance will be degraded.

    You could also use AD9689 a 14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter.

  • Hi,

    Thanks for your answer, unfortunately the AD9689 is a dual channel ADC which cost twice the price of the AD9699. This does not suit our application were cost is an important parameter.

    By looking at the curve you provided the SNR degradation seems limited (1dB of degradation over 700 MHz), and may probably still fit our application. Do you have have by any chance a figure about the expected performance degradation if we use it with a sampling frequency of 2000MHZ ?

    Best regards