AD9253 Data Alignment in Test Modes

 Hi jake24 ,

Thank you for your interest in AD9253.

Your query is acknowledge, give us sometime to check on it.

Thanks.

Hi jmoreno5, 

Have you found any additional information on this issue?

Hi jake24 ,

Thank you for your patience and apologies on delay response as we just came from holiday break.

As for the Data alignment of ADC core during Output test mode, when the Output test mode is enabled, the analog section of ADC is disconnected from the digital back-end blocks and the test pattern is run though directly from the output formatting blocks. This means that the ADC core is not feeding data to the digital back-end block, in case that there is data coming from the ADC core, this is being ignore during this mode.

Thanks.

Hi jmoreno5,

I understand that the ADC core is disconnected in test mode.  What I'm trying to understand is the statement in the datasheet:

Data from the output test modes are not necessarily time aligned from channel to channel.

Does that mean if I set the test mode to 0x0001 "Midscale short" I might get the expected value (0x80) on some channels and a shifted version of it like 0x40 or 0x01 on others?   

I would like to use this mode to verify that I'm capturing the data properly before switching to the analog core.   But if each channel is aligned differently, are any of them guaranteed to maintain their alignment once I switch back to the analog core?

Hi jake24 ,

Yes, you might notice some data misalignment from channel to channel during output test mode specially if you check it with  Checkerboard Output and once you disable the Output test mode thru register 0x0D, data alignment will be restored and the data from the ADC core is being transmitted in normal functional mode.

See below capture showing the output test mode using checkerboard output in 4 channel which show the data misalignment:

Below capture shows the single 10MHz input split to 4 channel transmitted from the ADC core in normal functional mode which guaranteed that the data alignment are being restored in normal mode.

Hope this clears it out.

Thanks.

Hi jake24 ,

Yes, you might notice some data misalignment from channel to channel during output test mode specially if you check it with  Checkerboard Output and once you disable the Output test mode thru register 0x0D, data alignment will be restored and the data from the ADC core is being transmitted in normal functional mode.

See below capture showing the output test mode using checkerboard output in 4 channel which show the data misalignment:

Below capture shows the single 10MHz input split to 4 channel transmitted from the ADC core in normal functional mode which guaranteed that the data alignment are being restored in normal mode.

Hope this clears it out.

Thanks.