Input is getting damaged? Inputs creating additional unsymmetric bias/offset

Hi ChristianSE 

Thanks for using AD9254.

Although Single-Ended Input Configuration is not recommended, it is possible as long as the input voltage swing is within the AVDD supply.

In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing.

If the source impedances on each input are matched, there should be little effect on SNR performance.

Some comments on your schematic, the CML pin 34 should be decoupled to ground with a 0.1 μF capacitor

ChristianSE said:

Why is in the datasheet written, that VCM = 0.55 × AVDD, why not 0.5 x AVDD?

Setting the device such that VCM = 0.55 × AVDD is recommended for optimum performance.

Hello,

A few recommendations to consider while looking at the schematic.
1) The voltage drop across L8 choke inductor is significant causing the the supply voltage seen at AVDD to be 1.64 V ..............which is out of the device specification supply range.  Suggest shorting out inductor for now and then replace (if needed for additional supply filtering) with a ferrite inductor that has far lower DC resistance.

2) Optimize the voltage divider ratio formed by R72_R75 and R84_R85 so that the voltage seen at ADC input is near the desired 1 V common-mode (i.e. 0.55 x AVDD).  To optimize..............first disconnect the the single-ended input from the input and then place 0 ohm resistor for R17 so that the this circuitry is perfectly symmetrical to the one looking out from the VIN- input back into the RC network.  In other words, VIN+ and VIN- (looking back into each of its RC networks must be the same.

Once this is done....the common-mode voltages seen at VIN+ and VIN- should be similar albeit lower than the desired 1 V common-mode.   Reduce R72 and R84 value to say 750 ohms to determine if how much the common-mode voltage is increased.  Note, this may be a little trial-in-error to hone in value that results in a common-mode value that is now closer to the desired 1 V.  

Note that the ADC input produces clock feedthrough that is symmetric on each of its inputs that is forced back into these RC networks hence causing a DC offset  thus the importance to making each of these RC networks symmetrical

3) Now reconnected the single-ended input  to the ADC circuitry and remove the R17 0 ohm resistor.  Ideally the input source is an op amp providing a low source impedance (i.e. acting like a 0 ohm resistor) such that it keeps the symmetry that we forced in step 2. If DC offset is still large............one can rescale  the values of R72_R75 and R84_R85 by 1/2 while keeping the same ratio to see if this reduces DC offset.  

Thanks for the answer.
I didn't see, that the AVDD is already out of range. This is really a major issue. I recognized already the huge drop, but did not check the spec on that. So, thanks a lot for this hint.

That single ended is not the best for performance is well known. For our applications it's best choice.

To all the other symmetrical input biasing. That's completely understand. The problem right now is, that it is working and the bias is symmetric, but after a while of operation, the input biasing is getting unsymmetric.

First we will now guarantee, that the AVDD is in the specified range.
Maybe that's all the magic, that is happening. Due to out of spec range, something is happening...

Will take some time, because I don't have the hardware right now on my table and will be shortly in vacation for a longer time...

Thanks for the moment.