Hello,
I would like to ask how to choose the values of RC in the input pins. I think it's better to refer to the datasheet but I could not find relative data.
The circuit is for baseband application.
Thanks for any suggestion.

AD9252
Not Recommended for New Designs
The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size,
and ease of use. Operating...
Datasheet
AD9252 on Analog.com
Hello,
I would like to ask how to choose the values of RC in the input pins. I think it's better to refer to the datasheet but I could not find relative data.
The circuit is for baseband application.
Thanks for any suggestion.

Hi yz077
Thanks for your interest in AD9252.
This is to acknowledge your query, kindly give us some time to check on this.
Hello,
The RC network forms a 1st order low pass filter as well as limits some of the "charge-kick" back from the AD9252 sampling network. The frequency response plot of a 1st order normalized response (i.e -3 dB cut-off called Fc = 1) is shown below with the 2nd plot being a zoomed in plot of the 1st plot with horizontal axis being NOT logarithmic. Based on the zoomed in response, one could select the filter to have a -3dB cut-off frequency of 4x the Nyquist zone so that the attenuation at edge of the 1st Nyquist zone (baseband region) provides only -0.25 dB magnitude attenuation and a phase shift of 15 degrees (Yellow Line).
For the AD9252 with a sampling rate of 50 MSPS, the 1st Nyquist zone extends from DC to 25 MHz. Based on statements above.......the low pass filter would be designed to have cut-off of 4x the Nyquist zone or 100 MHz. Looking at the figure 36 diagram, the resistor value is typically set in range of 25 to 50 ohms (i.e. evaluation board sets it to 43 ohms with 10+33 ohm resistors). For simplicity, we will set resistor value to 50 ohms so we can determine value of total "C" value required for cut-off of 100 MHz. For the differential input above, the total "C" value is equal to C value in parallel with 2*CDIFF..............recalling that if one breaks CDIFF into two series capacitance that each value of these capacitances would need to have value of 2*CDIFF so that series combination remains equal to CDIFF.
Recall that cut-off frequency, Fc , of RC filter is equal to 1/ (2*pi*R*C) where C in this case is "total" C for our analysis. Rearranging equation and solving for C results in equation of 1/(2*pi*R*Fc). Substituting 50 ohms for R and 100 MHz for Fc............the total "C" value is approximately 32 pF. Recall this value represents C+ 2*CDIFF in figure 36. If we set C to 8 pF than CDIFF will need to be 12 pF to satisfy this equation.
Lastly, one can not ignore that the differential ADC input of the AD9252 has 7 pF of input capacitance as shown in specification of datasheet that will contribute to this overall CDIFF. As a result.........the actual value of the physical capacitance for PCB's CDIFF will need to be 5 pF ( = 12 pF - 7 pF) to account for ADC capacitance.
So answer to your question is set R=25 ohms, C=8.2 pF and CDIFF=5.1 pF for a Fc of 100 MHz.


