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AD9642 Recommended for New Designs
The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications...
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AD9642 on Analog.com

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Why is the AD9642BCPZ-250 not outputting DCO?

		
	
				

			

									
					    korea.bro
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Sep 12, 2024 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Datasheet/Specs

    		        		            		    
Product Number:  AD9642  

    		        		    		    

		    		    
		    			

			    
I am using an LVDS oscillator (DSC1103CL3-250.0000T) as the CLK input for the AD9642. However, the AD9642 is not outputting the DCO signal.


I looked through the register map in the datasheet and couldn’t find any option like “DCO Enable.” Is there any specific reason why the DCO is not working?


Could you help me understand why this might be happening?




 

			

			
									
		                             
                        

    

                                            
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                on Sep 13, 2024 11:14 AM
            
            
						
			            		
    
		
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    Hello,
    

    Please verify the following information:
    

    1) Ensure AVDD and DRVDD supplies are at 1.8 V at the device pins.
    

    2) Ensure that the CLK inputs have a DC bias input of 0.9 V  with a differential clock signal exceeding 0.3 Vpp being present.
     
    

    3) Ensure that the device is not in a power-down or standby state.

     
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 14, 2024 12:54 AM
            
            
												
						in reply to PMH2023
					
										
			            		
    
		
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    1. As shown in the circuit diagram, AVDD and DVDD are properly inputting 1.8V. I tested register Read and Write via SPI communication.
    

    2. This is a picture of the input to the CLK pin.
    

    Diff is 420mVpp, single is 210mVpp. The frequency is input as 250MHz.
    

     
    

    3. The 0x08 register has never been changed from its initial value.
    Should I set it to 0x00 again?
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 14, 2024 3:01 PM
            
            
												
						in reply to korea.bro
					
										
			            		
    
		
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    Hello,

    You can try resetting via SPI but typically these devices have a Power-on-Reset.  

    Note..........a software reset of all SPI registers to default can be done by setting 0x00 to 0x3C.

    Lastly......other than what I stated above , I am not sure what could be cause unless the voltage levels you show are still insufficient for the CLK receiver input (albeit they look above datasheet spec).  On the last point.....one can try to increase termination resistor to 200 ohms to get an increase in voltage swing from LVDS clock source.

    If this does not work..............someone from ADI factory will need to provide further assistance to you.

     
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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