Dear all,
I have a board with 3 AD9697 running at 1280 Sampling/second. The readout is done with a kintex ultra-scale (xcku035)
After initialization, I read samples and every thing is fine. Without signal, I got a baseline with an RMS of 500 uV:
The problem is that after some times (few minutes) I got this kind of patterns:
where clearly some bits are corrupted in ADC3, few also in ADC2 and none in ADC1.
If I redo the init procedure, everything is fine again.
There are few points to know:
- ADC3 is the farest to the FPGA (~12 cm) and closest to the clock generator.
- If I send patterns (ramp, midscale, full scale, custom, etc.) in the ADC, I do not see any corruption
- The PLL lock status bits are correct (ADC PLL-reg 0x056F and JESD PLL-reg 0x1262)
- Playing with pre-emphasis does not change anything
- Using scrambling or not gives exactly similar patterns
This latter point makes me think that the problem is inside the ADC before the serialization otherwise I would see different corruption patterns with or without scrambling.
I would like to know if this kind of behavior rings some bell to any of you...
Thank you very much for any advice.
Best regards
Marc
