Clock Source Recommendation and Additional Required Components

Hello,

Considering that simplicity of your application (i.e. no synchronization, single converter IC to FPGA), one can likely use a PLL IC with on-chip VCO to reduce cost of clocking solution.    When selecting PLL/VCO IC's, one may also want to consider the jitter requirement in the target application since clock jitter degrades the SNR performance at higher frequencies and large-scale input signals.  The AD4355-2 may be a suitable solution (ADF4355-2 Datasheet and Product Info | Analog Devices) if jitter requirements can tolerate 150 fsec/rms.  Note that target application may also have phase noise requirements (which relate to jitter) thus one may need to consider phase noise as an alternative way of looking at the PLL/VCO clock generation specs.

The other issue is that the clock reference used by the ADF4355 REFIN must also be used by the FPGA IC which has its own internal PLL to generate the SERDES  clock equal to the lane JESD lane rate.  The REFIN clock frequency often can be made equal to SERDES RATE/(40*N) where N=1,2,3,4 such that REFIN clock frequency also meets the AD4355's max REFIN clock frequency.  

Hi Jonathan,

I agree with Paul's comments. It gives great insights. 

My comments will be more focused on the HMC7044. 

The phase noise performance of the HMC7044 is better compared to AD9528. 

Both these parts contain a PLL, a VCO, and a clock distribution section. However, HMC7043 only includes a clock distribution section. 

If I understand your requirements, HMC7044 is more suitable as it can provide a clock to ADC, a clock to FPGA, and system reference signals (SYSREF) to ADC and FPGA  with the help of the individual dividers along the outputs. 

HMC7044 includes a VCO that can operate between 2.4GHz and 3.2GHz, you can generate a 1GHz or 1.3GHz clock for ADC operation. 

To generate a desired frequency using the PLL and VCO of the HMC7044, you need a reference signal. 

Reference signals can be provided externally or by using a crystal. Depending on your phase noise requirements, a simple Crystal oscillator such as CCHD-950-100 can provide the needed reference signal to lock the PLL and VCO HMC7044.  After generating the desired clock frequency, you can use the output dividers to create an FPGA reference, JESD204 SYSREF Signals.

You can simulate the phase noise performance and calculate the desired divider values for your clocking architecture using ADISimCLK. 

 Thanks,

Emrecan