Our AD9250 JESD link to the FPGA is very unreliable. We can establish a link but the data received over it is interrupted by a 250 MHz sine wave that appears intermittently but with some consistency. This occurs on multiple boards using the same configuration so it is presumably something in our initialisation process. Having probed around, this sine wave is being generated by the AD9250, not coupled on from elsewhere. We can see the CGS and then ILAS and the deframer beginning to receive data, but the data is then interrupted by this sine wave that presents itself on our ILA as 0x4A4A4A4A held for 26 clock cycles.
- AD9250 running at 250 MSPS with 250 MHz clock (the clock looks fine on the scope).
- Zynq Ultrascale+ FPGA receiving JESD, running with 125 MHz clock (also looks fine).
- JESD subclass 1 with continuous SYSREF at 1.25 MHz (also looks fine) , L=2, K=32, m=2.
- It does not seem to matter whether the AD9250 is configured to output a ramp, checkerboard or other pattern.
- The power rails look to be fine and are as per the layout guidance in the datasheet.
I did find one reference here www.analog.com/.../JESD204B-link-debug.pdf suggesting that the AD9250 puts out D10.2 characters during link initialisation which is unusual. Analog Devices can you verify whether this could be relevant?
Has anyone else experienced this? I will attach images of our scope detecting the transition from JESD to the sine wave. The sine wave usually lasts around 200 ns and then JESD returns and the problem repeats..
Thanks in advance.
