How to calculate the clock frequency required by FPGA and AD9695 to start jesd204b ?

Question

I want to calculate the following clock values ​​for the AD9695 
 F(Number of Octets)=4. 
 L(Number of lanes)=4. 
 K(number of frames )=32. 
 S( number of samples per converter) =1, 
 M(Number of Converter)=2. 
 N'(number of bits per sample)=16. 
 Decimation Ratio=1. 
 Fadc=1.3GHZ. 
 Fout=Fadc / Decimation Ratio=1.3GHZ. 
 Lane rate=(M*N'*(10/8)*Fout)/L=> Lane rate =13Gbps. 
 REF_CLK= CORE_CLK=Fc=Frame Clock=lane rate/(10*F)=>325MHZ. 
 SYSREF_CLK =Fc/(S*K)=325/32=10.15725MHZ. 
 
 I have not found a specific formula for calculating SYSREF_CLK, CORE_CLK and SYSREF_CLK. are my calculations correct?

JAlipio · Accepted Answer

Hi OHBsystemag 
 Thanks for your interest in AD9695. 
 OHBsystemag said: REF_CLK= CORE_CLK=Fc=Frame Clock=lane rate/(10*F)=>325MHZ 
 The REFCLK should be 650 MHz, you may refer to the wiki user guide EVALUATING THE AD9695/AD9697 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki] for the REFCLK calculation. 
 
 OHBsystemag said: SYSREF_CLK =Fc/(S*K)=325/32=10.15725MHZ. 
 While for the SYSREF, it should be 40.625 MHz with ADC Clock = 1.3 GHz.)

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How to calculate the clock frequency required by FPGA and AD9695 to start jesd204b ?

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