glitches in samples

Hi jpathiku 

Thanks for your interest in AD9695.

Your query is acknowledged. Kindly give time for the product owner (s.ilke ) to look into this and provide their response.

the settings are:

sample rate 800 MHz, full bandwidth mode. two lanes used. data rate on each lane is 16 Gb. The receiver eye is good. no out of table 8B10B errors.

lane 0 and 2 are used. they are mapped to logical lanes 0 and 1. unused lanes powered down. the initialization C code snippet is given below. (i have added resets to 0x0571 and 0x1 after searching through answer records. but makes no difference). scrambling on or off makes no difference.

  adc_spi_write(0x0,0x81);// soft reset
  Sleep(10);

  adc_spi_write(0x05b0,0x44);// shutdown lanes 1 and 3 (0 & 2 are used)
  adc_spi_write(0x05B5,0x01);// logical lane 1 is on Lane 2
  adc_spi_write(0x05B3,0x02);// logical lane 2 is on Lane 1 (not used)

  adc_spi_write(0x027A,0x00);// SPORT over JESD disabled
  adc_spi_write(0x055A,0x00);// control bit 2 tie low
  adc_spi_write(0x0572,0x10);// CMOS SYNCINB
  if(faci_on)
  {
    adc_spi_write(0x0571,0x15);// bit 1; frame alignment character insertion enabled
    adc_spi_write(0x0571,0x14);// bit 1; frame alignment character insertion enabled
  }
  else
  {
    adc_spi_write(0x0571,0x17);// bit 1; frame alignment character insertion disable
    adc_spi_write(0x0571,0x16);// bit 1; frame alignment character insertion disable
  }

  adc_spi_write(0x1A4C,0x0f);// Buffer Current 300 uA
  adc_spi_write(0x1A4D,0x0f);// Buffer Current 300 uA
  adc_spi_write(0x1B03,0x02);// Additional settings for Buffer Current 300 uA
  adc_spi_write(0x1B08,0xC1);// Additional settings for Buffer Current 300 uA
//  adc_spi_write(0x1B10,0x00);// Additional settings for Buffer Current 300 uA (default)

  // L = 2, M = 2, F = 2, K = 32 , CS = 0, N' = 16
  if(scramble_jesd)
    adc_spi_write(0x058B,0x81);// L = 2 lanes per Link; bit 7 is scrambler on
  else
    adc_spi_write(0x058B,0x01);// L = 2 lanes per Link; bit 7 is scrambler off
  adc_spi_write(0x056E,0x30); // for 13.5+ Gbits/sec rate
  adc_spi_write(0x058C,0x01);// F = 2

  adc_spi_write(0x1,0x02); // soft reset the data path; self clearing
  Sleep(10);
  // JESD startup
  adc_spi_write(0x1228,0x4F);
  adc_spi_write(0x1228,0x0F);
  adc_spi_write(0x1222,0x00);
  adc_spi_write(0x1222,0x04);
  adc_spi_write(0x1222,0x00);
  adc_spi_write(0x1262,0x08);
  adc_spi_write(0x1262,0x00);

regards,

joseph

the settings are:

sample rate 800 MHz, full bandwidth mode. two lanes used. data rate on each lane is 16 Gb. The receiver eye is good. no out of table 8B10B errors.

lane 0 and 2 are used. they are mapped to logical lanes 0 and 1. unused lanes powered down. the initialization C code snippet is given below. (i have added resets to 0x0571 and 0x1 after searching through answer records. but makes no difference). scrambling on or off makes no difference.

  adc_spi_write(0x0,0x81);// soft reset
  Sleep(10);

  adc_spi_write(0x05b0,0x44);// shutdown lanes 1 and 3 (0 & 2 are used)
  adc_spi_write(0x05B5,0x01);// logical lane 1 is on Lane 2
  adc_spi_write(0x05B3,0x02);// logical lane 2 is on Lane 1 (not used)

  adc_spi_write(0x027A,0x00);// SPORT over JESD disabled
  adc_spi_write(0x055A,0x00);// control bit 2 tie low
  adc_spi_write(0x0572,0x10);// CMOS SYNCINB
  if(faci_on)
  {
    adc_spi_write(0x0571,0x15);// bit 1; frame alignment character insertion enabled
    adc_spi_write(0x0571,0x14);// bit 1; frame alignment character insertion enabled
  }
  else
  {
    adc_spi_write(0x0571,0x17);// bit 1; frame alignment character insertion disable
    adc_spi_write(0x0571,0x16);// bit 1; frame alignment character insertion disable
  }

  adc_spi_write(0x1A4C,0x0f);// Buffer Current 300 uA
  adc_spi_write(0x1A4D,0x0f);// Buffer Current 300 uA
  adc_spi_write(0x1B03,0x02);// Additional settings for Buffer Current 300 uA
  adc_spi_write(0x1B08,0xC1);// Additional settings for Buffer Current 300 uA
//  adc_spi_write(0x1B10,0x00);// Additional settings for Buffer Current 300 uA (default)

  // L = 2, M = 2, F = 2, K = 32 , CS = 0, N' = 16
  if(scramble_jesd)
    adc_spi_write(0x058B,0x81);// L = 2 lanes per Link; bit 7 is scrambler on
  else
    adc_spi_write(0x058B,0x01);// L = 2 lanes per Link; bit 7 is scrambler off
  adc_spi_write(0x056E,0x30); // for 13.5+ Gbits/sec rate
  adc_spi_write(0x058C,0x01);// F = 2

  adc_spi_write(0x1,0x02); // soft reset the data path; self clearing
  Sleep(10);
  // JESD startup
  adc_spi_write(0x1228,0x4F);
  adc_spi_write(0x1228,0x0F);
  adc_spi_write(0x1222,0x00);
  adc_spi_write(0x1222,0x04);
  adc_spi_write(0x1222,0x00);
  adc_spi_write(0x1262,0x08);
  adc_spi_write(0x1262,0x00);

regards,

joseph

back after holidays - a fresh look showed that samples were sliced wrongly. (the ms byte of of one sample was combined with the ls byte of adjacent sample)  and this causes the "glitch"

in hindsight, the issue is somewhat "obvious" and it is curious that this forum or the ADI staff has not offered any help in this instance.

hi,

What speed grade of AD9695 do you use, 625 MSPS of 1300MSPS?

can you please check JESD link parameters? With L=2, M = 2, N' = 16 in full bandwidth mode,

the lane rate becomes 12.5 Gbps at 625 MHz clock and 26 Gbps (>max lane rate 16G) at 1300MHz clock but the register 0x056E is set for 13.5G+

when 0x0550 is set x0F, it is ramp output like below.

clock = 625MHz

full bandwidth mode

L=2, M = 2, N' = 16

lane rate 12.5Gbps (0x056E is set to 0x00 for lane rate 6.75 Gbps to 13.5 Gbps)

sample rate was 800Msps. using two lanes at 16Gb