AD9528
Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
Datasheet
AD9528 on Analog.com
AD9083
Recommended for New Designs
The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time S-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter...
Datasheet
AD9083 on Analog.com
Hello
I have connected AD9083 sysref input to AD9528 out, similar to the evb example PCB (AD9083EBZ).
Now, I found engineer_Note_AD9083 SYSREF interface with LVDS, that suggest different connectivity with level shift circuit.
And the EN also suggest writing to 0xD4C (sysref termination) which is not in the datasheet.
Currently my FPGA recognize the sysref signal but the AD9083 not (reading 0x27E[3:1] return 0).
Is it because of the level shifter? my device reference clock is 200MHz.
Thanks
Hi NRW ,
Thank you for reaching out.
The EVB sysref connection is the typical example of AC coupling scheme for sysref, however if you are planning to use n-shot or periodic sysref we recommend to use what was stated in the engineering note using LVDS to sysref common mode level shift and disable the internal sysref termination with register address 0xD4C (this will be included in the next datasheet revision).
As for 0x27E readout i may need to get back to you as i need to check this out further.
Hi NRW ,
I had the same exact issue. If you still haven't found a solution, check my latest reply in my post here:
RE: SYSREF capture on AD9083EBZ
Kind regards,
Cekobidonq