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Input Clock Divider (1:6) and DCS use

Category: Hardware
Product Number: AD9269

Dear Support Team,

We are currently using an AD9269BCPZ-80 (from Analog Devices). We are entering a 70MHz differential clock signal to the AD9269 and we are using the Input Clock Divider (figure attached down below) to divide by 6 for downsampling purposes. We would like to know if the division is exact (i.e., if the result is 70/6) or if some kind of approximation or truncation is done by the device (such as 11.7MHz, 11.67MHz, 11.667MHz, etc). This is important because we are working with an FPGA in the same clock domain as the sampling frequency, and we need it to be as precise as possible. In case it is not an exact number, is there any possibility of obtaining it? Any extra bit that needs to be modified?

Plus: We have also found in the datasheet we should activate the DCS because of the division by 6. We understand that the ADC would be less sensitive to noise and distortion caused by variations in the clock duty cycle with DCS. Is it correct? By activating it, also can we make the clock more precise? In other words, can we get it as close as possible to the ideal 70/6 MHz for sampling frequency?


Your assistance in resolving this matter would be greatly appreciated.

Thank you for your attention to this request.

Best regards,

agf7,

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  • Plus: we have seen that the DCS shares pin with SDIO. We understand that we can only use the DCS on this pin if we do not activate the SPI mode, and if we are working with SPI, we should use the corresponding bit in Register 0x09 (Clock). Is this correct? Or are we missing something? Any clarification is welcome.

    Thanks again,

  • Hello,

    The ADC clock divider is "exact" so divider setting of 6 will result in an ADC clock of exactly FCLK/6.   The DCS must be used when the minimum internal ADC clock high or low cannot be met which is 5.625 nsec for the AD9269-80 assuming 80 MSPS operation with 45/55 duty cycle.  In you case, operating at FCLK of 70 MHz will ensure that the divided down clock high/low can be met.  That said...............one can try enabling the DCS by setting bit[[0] of Reg 0x09 and see if does make a difference.  


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  • Hello,

    The ADC clock divider is "exact" so divider setting of 6 will result in an ADC clock of exactly FCLK/6.   The DCS must be used when the minimum internal ADC clock high or low cannot be met which is 5.625 nsec for the AD9269-80 assuming 80 MSPS operation with 45/55 duty cycle.  In you case, operating at FCLK of 70 MHz will ensure that the divided down clock high/low can be met.  That said...............one can try enabling the DCS by setting bit[[0] of Reg 0x09 and see if does make a difference.  


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