Dear Support Team,
We are currently using an AD9269BCPZ-80 (from Analog Devices). We are entering a 70MHz differential clock signal to the AD9269 and we are using the Input Clock Divider (figure attached down below) to divide by 6 for downsampling purposes. We would like to know if the division is exact (i.e., if the result is 70/6) or if some kind of approximation or truncation is done by the device (such as 11.7MHz, 11.67MHz, 11.667MHz, etc). This is important because we are working with an FPGA in the same clock domain as the sampling frequency, and we need it to be as precise as possible. In case it is not an exact number, is there any possibility of obtaining it? Any extra bit that needs to be modified?
Plus: We have also found in the datasheet we should activate the DCS because of the division by 6. We understand that the ADC would be less sensitive to noise and distortion caused by variations in the clock duty cycle with DCS. Is it correct? By activating it, also can we make the clock more precise? In other words, can we get it as close as possible to the ideal 70/6 MHz for sampling frequency?
Your assistance in resolving this matter would be greatly appreciated.
Thank you for your attention to this request.
Best regards,
agf7,
