AD9689 with VC709 FPGA REFCLK problem

Question

i want to test AD9689-2600EBZ by using my XILINX FPGA VC709.but i dont know how to give FPGA the REFCLK signal which used in JESD204B ip core.i can't find any REFCLK input on the AD9689-2600EBZ.there is only a sma connector named GLBLCLK TO FPGA.BUT the pin is not support REFCLK. 
 when i directly input REFCLK to FPGA GBTREFCLK sma pin,the vivado report a place error. 
 so i would like to know what the right method is to allocate the clock and signal to AD9689-2600EBZ and VC709 FPGA. 
 Thanks & Regards

s.ilke · Accepted Answer

Hi, 
 We use ADS7-V2 or ADS8-V1 FPGA boards to evaluate AD9689-2600EBZ. for which there is user guide at the link below. Sampling clock is connected to AD9689-2600EBZ and reference clock is connected to the FPGA board. 
 EVALUATING THE AD9208 / AD9689 / AD9699 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki] 
 You should be able to XILINX FPGA VC709 if it is pin compatible to FMC connector on ADS7-V2 / ADS8-V1. 
 Regards)

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AD9689 with VC709 FPGA REFCLK problem