i am using jesd204b interface between ad9699 and FPGA.
my jesd parameter is as below.
Fs=2949.12MHz, Fout = 491.52MHz(complex decimation 6 mode), F=1, K=32, L=4, M=2, S=1
i have some questions about ad9699 jesd204b latency. and i want to know if my understanding is correct.
1. I think Pipeline Latency in datasheet is same as END to END total latency of AD9699. Does Pipeline Latency in datasheet mean ADC Core latency + DSP(DDC in AD9699) latency + JESD204B transport layer in AD9699 latency?
2. as far as i know, for correct deterministic latency and K*F parameters, Link Latency(ADC(TX) input of Serializer to FPGA(RX) output of Elastic Buffer) is needed. then, for Link Latency, do i have to only consider Table 37.Latency Through JESD204B Block?
3. when i use DDC in ad9699(not adc full bandwidth mode), Does encode clock mean adc sampling clock(Fs)? not DDC clock in ad9699(Fout)?
thanks