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QPLL TX buffer underflow error, status: 0x61

Category: Hardware
Product Number: AD9081

Hi,

I am using AD9081 EVM running with Xilinx KCU105(Kintex ultrascale FPGA). Design is migrated from analog device provided HDL and no-os driver for VCU118. After loading the elf file, I am getting the QPLL TX buffer underflow error, status: 0x61 on serial port.

Log file for the serial port is attached.

Kindly suggest the changes to come out this issue.


Hello
rx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_tx_link_status_print: JESD RX (JTX) Link1 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
DAC IRQ status 0xf043000000
IRQ_STATUS0: 0x0
ad9081_multichip_sync:2
ad9081_multichip_sync:3
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
tx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:527:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:534:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL TX buffer overflow error, status: 0x61
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
AD9081 Rev. 3 Grade 10 (API 1.2.2) probed
tx_jesd status:
        Link is enabled
        Measured Link Clock: 249.998 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 10000.000 MHz
        Lane rate / 40: 250.000 MHz
        LMFC rate: 7.812 MHz
        SYNC~: asserted
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd status:
        Link is enabled
        Measured Link Clock: 249.998 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 10000.000 MHz
        Lane rate / 40: 250.000 MHz
        LMFC rate: 7.812 MHz
        Link status: CGS
        SYSREF captured: Yes
        SYSREF alignment error: No
tx_dac: Successfully initialized (249996948 Hz)
rx_adc: Successfully initialized (249996948 Hz)
Running TinyIIOD server...
                          If successful, you may connect an IIO client application by:
                                                                                      1. Disconnecting the serial terminal you use to view this message.
                                                                                                                                                        2. Connecting the IIO client application using the serial backend configured as shown:
        Baudrate: 115200
                                Data size: 8 bits
                                                        Parity: none
                                                                        Stop bits: 1
                                                                                        Flow control: none

Thread Notes

  • Moved to FPGA Reference Design community for their reply.

  • Hi,

    Have you checked out this thread? RE: AD9082-FMCA-EBZ, QPLL RX buffer underflow error  With focus on the comment I linked, but not only.

    Best regards,
    Iulia

  • Hi,
    I have checked the thread as mentioned in the link.

    Now I changed the QPLL0 used for the Tx link to CPLL as in the app_JESD.c file

    #ifdef TX_XCVR_BASEADDR
    struct adxcvr_init tx_adxcvr_init = {
    .name = "tx_adxcvr",
    .base = TX_XCVR_BASEADDR,
    /*.sys_clk_sel = ADXCVR_SYS_CLK_QPLL0,*/
    .sys_clk_sel = ADXCVR_SYS_CLK_CPLL,
    .out_clk_sel = ADXCVR_REFCLK_DIV2,
    .lpm_enable = 0,
    .lane_rate_khz = tx_lane_clk_khz,
    .ref_rate_khz = reference_clk_khz,
    };
    #endif

    #ifdef RX_XCVR_BASEADDR
    struct adxcvr_init rx_adxcvr_init = {
    .name = "rx_adxcvr",
    .base = RX_XCVR_BASEADDR,
    /*.sys_clk_sel = ADXCVR_SYS_CLK_CPLL,*/
    .sys_clk_sel = ADXCVR_SYS_CLK_CPLL,
    .out_clk_sel = ADXCVR_REFCLK_DIV2,
    /*.lpm_enable = 1,
    .lane_rate_khz = rx_lane_clk_khz,
    .ref_rate_khz = reference_clk_khz,*/
    .lpm_enable = 1,
    .lane_rate_khz = rx_lane_clk_khz,
    .ref_rate_khz = reference_clk_khz,
    };
    #endif



    TX status is now in data and DACs are working. However, the Rx link status is still in the CGS stage.


    The serial terminal log is below:


    Hello
    rx_adxcvr: OK (10000000 kHz)
    tx_adxcvr: OK (10000000 kHz)
    ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
    tx_adxcvr: OK (10000000 kHz)
    ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0xF lanes in DATA
    ad9081_jesd_tx_link_status_print: JESD RX (JTX) Link1 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
    DAC IRQ status 0xf043000040
    AD9081 Rev. 3 Grade 10 (API 1.2.2) probed
    tx_jesd status:
    Link is enabled
    Measured Link Clock: 249.997 MHz
    Reported Link Clock: 250.000 MHz
    Lane rate: 10000.000 MHz
    Lane rate / 40: 250.000 MHz
    LMFC rate: 7.812 MHz
    SYNC~: deasserted
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment error: No
    rx_jesd status:
    Link is enabled
    Measured Link Clock: 249.998 MHz
    Reported Link Clock: 250.000 MHz
    Lane rate: 10000.000 MHz
    Lane rate / 40: 250.000 MHz
    LMFC rate: 7.812 MHz
    Link status: CGS
    SYSREF captured: Yes
    SYSREF alignment error: No
    tx_dac: Successfully initialized (249998474 Hz)
    rx_adc: Successfully initialized (249998474 Hz)
    Running TinyIIOD server...
    If successful, you may connect an IIO client application by:
    1. Disconnecting the serial terminal you use to view this message.
    2. Connecting the IIO client application using the serial backend configured as shown:
    Baudrate: 115200
    Data size: 8 bits
    Parity: none
    Stop bits: 1
    Flow control: none


    Kindly suggest what can be done.