I am working on a design in which an FGPA reads the output of a 12-bit ADC at 40MHz (AD9236) after amplifying the signal by an AD8132 fully differential amplifier. After summing the input in specific time windows the data is stored on an SDRAM. The problem is that the operation of SDRAM logic makes noise on ADC. To regenerate the problem I have deleted the SDRAM logic from my code and just toggled some random pins of SDRAM for a certain amount of time to find out the reason. It seems toggling pins are responsible for coupling noise to the power rails. Different LDOs are used for each power rail with ferrites at outputs. I have added several bypass/decoupling caps to ADC power rails like Analog, Digital, and Vref pins which seem to have no or less impact on the issue. I have also used separate power planes for analog and digital parts and a solid ground layer. Increasing the gain of the amplifier makes the situation worse.
Here are some readings of ADC output at low and high gain. The pins are just toggled between sample 500 and 600 for hundred times. This behavior is also present when there is no amplifier in the circuit.
LOW gain:
HIGH gain:
The schematic of AD9236:
The layouts:
