DAC NCO synchronization

Hello,

Please refer to the technical application note as well as UG1578 for more details on how to to perform multi-chip synchronizaiton.

   https://www.analog.com/en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html

https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf

Thanks for your help.

In the user guide is this statement: "The default method is to reset the NCOs relative to an internal synchronization
signal, where the rising edge of the DDSM_FTW_LOAD_REQ bit (Register 0x01CA, Bit 0) triggers an update on the next rising edge of the
internal synchronization signal."

The "internal synchronization signal" is left somewhat vague. I know that the external trigger is SYSREF. However, the internal trigger is not defined. Is it necessary to generate the "internal synchronization signal", or is that done automatically?

Hello,

The excerpt below provides more insight in the use of SYSREF to reset the NCO phases along with API required for this purpose.

With regard to "internal synchronization signal"...................this signal is generated when operating in Subclass 0 modes and is generated during the initialization phase when configuring the JESD204B/C interface via an API.

Thanks, again, for your quick response. You have been most helpful.

So, the internal synchronization signal occurs during JESD configuration. I am using the AD9081 with a ZCU102 under IIO. The JESD is done configuring well before my software starts talking to the 9081. Therefore, it seems that generating a external SYSREF is the most likely method for synchronizing the NCO's, Is that how you see it?

Yes.........especially when multi-chip synchronization is involved with is typically the case in beam-forming consisting of many channels.