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latency question

Category: Datasheet/Specs
Product Number: AD9690

Hi

  1. According to table 4, pipeline latency is 55 clock cycles. Does this clock cycle means the clock which is from CLK+/CLK- pins? Does this pipeline represent the ADC+DSP latency?
  2. How to calculate the consumption time from analog signal inputting AD9690 to digital signal outputting from JESD204B lane?