latency question

Question

Hi 
 
 According to table 4, pipeline latency is 55 clock cycles. Does this clock cycle means the clock which is from CLK+/CLK- pins? Does this pipeline represent the ADC+DSP latency? 
 How to calculate the consumption time from analog signal inputting AD9690 to digital signal outputting from JESD204B lane?

PMH2023 · Accepted Answer

Hello,

The specification only refers to the ADC pipeline latency. The datasheet is lacking a section similar to what is shown in the AD9208 datasheet as shown below which would allow one to calculate total latency. Someone from factory would need to calculate latency for AD9690 since this section does not exist on the AD9690 datasheet.

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latency question