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AD9690 Recommended for New Designs
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low...
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AD9690 on Analog.com

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latency question

		
	
				

			

									
					    mashimaro
					
							

            
            			
				
									
											
			
			
				
  •  Analog Employees  

			
			
			    	
			                    
                
				                on Jan 28, 2024 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquired about the meaning of 55 clock cycles in the AD9690 pipeline latency and how to calculate the total latency from analog input to digital output. The final answer clarifies that the 55 clock cycles refer to the ADC pipeline latency, and the datasheet lacks a section to calculate total latency, similar to the AD9208 datasheet. A factory engineer would need to calculate the total latency for the AD9690.
                        	    

                
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Category: Datasheet/Specs

    		        		            		    
Product Number:  AD9690 

    		        		    		    

		    		    
		    			

			    
Hi


    

  1. According to table 4, pipeline latency is 55 clock cycles. Does this clock cycle means the clock which is from CLK+/CLK- pins? Does this pipeline represent the ADC+DSP latency?
    2. 

  2. How to calculate the consumption time from analog signal inputting AD9690 to digital signal outputting from JESD204B lane?
    3. 


			

			
									
		                             
                        

    

                                            
                 Datasheet/Specs
                
                                                    
                 ad9690
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
                 Standard High Speed A/D Converters
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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                on Jan 29, 2024 11:47 AM
            
            
						
			            		
      
		
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      Hello,

      The specification only refers to the ADC pipeline latency.  The datasheet is lacking a section similar to what is shown in the AD9208 datasheet as shown below which would allow one to calculate total latency.  Someone from factory would need to calculate latency for AD9690 since this section does not exist on the AD9690 datasheet.

       
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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