Category: Hardware
System shall have 5 DRx modules. Each module shall have its synthesizer (LTC6952 and ADF4368) to generate the JESD204B clocks and sampling clocks and 2 AD9209 chips, accounts to 8 Rx Channels per module. So, all these five DRx modules (40 Rx channels) have to be phase aligned.
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Clock- Distribution Module shall have on-Board OCXO to generate 120MHz which is then passed via power Divider(1:8) to provide 120 MHz clock reference to all the six Modules (5 DRx Modules (10Chips) + One controller Clock Modules) and unused ports are terminated.
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controller Clock Modules shall generate EZS-SRQ (SYNC or Sysref) to reset the dividers of LTC6952 and ADF4368 of all five DRx modules
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Each of the five DRx modules shall generate clocks required for ADC, JESD204B interface and 120MHz system clock for FPGA
- Kindly verify the power level once for a single module.
- LTC6952 shall have HD2 harmonic, does it have to be suppressed before feeding to AD9209 clock inputs?
- Kindly suggest VCXO part of frequency 600MHz. I am planning to use CVCO55CL-0575-0675. Is it fine?
Limitations:
1. All 120 MHz routed via RF Cable to five modules may have phase mismatch of max 3 degree
2. All sync signals routed via ethernet cables may have phase mismatch of max 5 degree across the five modules
3. 120MHz is from Clock-Distribution Module and SYNC is from controller Clock Modules, it may result in fixed phase-offset between SYNC from controller Clock module and 120MHz from Clock -distribution module
4. All these phase offset has to be compensated at ADF4368 and LTC6952 to meet the timing specifications to do divider reset
5. As per UG-1578, DC-Coupled sysref operation is supported as per Page. No: 29. In this design, we are planning to use one-shot sysref to reset the dividers. Does the configuration in Page.No:29 is applicable only for two-shot, four-shot sysref pulses or even it applies to single-shot sysref pulses
6. What is the minimum number of sysref pulses required to reset the dividers of AD9209 including NCO, LTC6952 and ADF4368. (i.e. Pulse width should be four times of Clock input of AD9209)
7.What is the use of NCO-subordinate sync in Multi-chip synchronization, even though one-shot sync shall be used to reset NCO
8. How to interface SYNC from LTC6952 to ADF4368 as the common -mode voltage in different (2.3V to 1.3V). As the SYNC signal is a one-shot waveform
9. Kindly share some application note to delay the clock output with reference to reference-signal phase mismatch. (If I have a 5-degree phase mismatch in reference clock, how much delay should I add in output clock)
All EZS-SRQ shall be dc-coupled from controller Clock Module to DRx Modules. Board-1 to Board-5 in clock scheme pdf is DRx Modules.
PDFs:
clock_scheme : With the list of components over the clock path
clock_scheme_divider settings : Dividers settings of synthesizer to generate onboard clock.
Added PDFs
[edited by: Sagar_BN at 5:43 PM (GMT -5) on 19 Jan 2024]
