Hello,
I'm designing zero IF receiver. I need to design baseband section with DC offset cancellation circuit similar to below:
I have not found good application notes or other material, which could help me to complete design. My ADC would be AD9963 and I'm planning to use ADA4937 or ADA4940 as driver.
Is there any recommendations for VGA and Gm?
Hello,
Input power up to 30 dBm is a very high requirement. LNA likely needs bypass to handle such strong level along with independent "fast" AGC if normal AGC is not fast enough to track blocker with fast envelope rise times to protect active circuitry from exceeding max ratings.
Anyways, not aware of any dedicated off the shelf "gm" block product that ADI (or other vendor) has so likely you will need to design your own differential servo loop using dual op amps per I and Q. One could configure the dual op amps as integrators sniffing the differential input to ADC via series resistors connected to the "-" terminal of op amp and a capacitor across the amplifiers output to "- terminal. Op amps + terminal should be tied to the common-mode of the ADC input voltage. Note the series resistors used to sense ADA4937 output can also broken into two resistors such that a differential capacitor could be included to roll-off any high frequency content appearing at ADA4937 to getting into the op amp inputs (especially if low bandwidth op amps are selected). The output resistors used to connect integrators to RxVGA input can be sized to provide enough DC compensation range required at RxVGA input while realizing that op amps output swing with this resistor value will determine compensation range. The noise that these amplifiers can inject back into the VGA input should also be considered. Highly suggest simulating circuit to optimize for your application.
The LTC5584 quad demod looks like an interesting product since it has "hooks" for IP2 and DC offset correction albeit it likely lacks instantaneous dynamic range required for your application. A super-het application may be more suited for high blocker level application since it does not require DC offset or IIP2 correction.
Good luck.
Hello,
It should be possible to only use the Rx portion since other unused portions can be powered down via bitfields assigned to the 24-bit configuration registers.
Note the following:
1) Product was released back in 2008. While it still is being sold, evaluation boards are no longer available should you preferred to explore how well this part works in your application.
2) In terms of factory applications support, it will also be likely limited given this products age.
P.S. I was involved in the product definition of this product (along with companion DAC/ADC product) targeted specifically at UHF RFID readers which are based on homodyne architecture with large CW signal always being present (to power RFID tag) and return signal from RFID tag being a serial bit stream having a spectrum centered about DC out to a few MHz depending on clock rate. During the initial power-up of the RFID, the Tx produces a CW tone that produces a large DC offset on the Rx I/Q output and one calibrates this DC offset prior to when the RFID tag provides its data stream.......hence DC offset correction is gated.
I have since retired and would not be in a position to provide apps support....................hence I highly suggest that you review the datasheet and determine if indeed this product fits your needs and you are comfortable designing this product into your application with negligible factory support (beyond what is stated in datasheet).
