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AD9209 Parameters

Category: Hardware

I am using AD9209 ADC for sampling 2700MHz of bandwidth 50MHz with sampling rate of 3.6GSPS and IQ data rate of 600MSPS per ADC (I data rate - 300MSPS and Q data rate – 300MSPS) with decimation factor of 12 and Internal Complex NCO. I will be using all four channels of ADC and all 16 JESD204B lanes.

1. Isolation across RX Channels

2. Frequency Flatness across RX channels

3. Noise Figure Value for Fin of 2.7GHz.Datasheet has for 300MHz I/P and with direct Ref clock

4. Spurious Signal Level for the top specifications (decimation and sampling frequency

5. ADC Architecture: Architecture 1 is single core ADC and Architecture 2 is interleaved ADC with two sub core

6. Is it okay to use Complex NCO as IQ demodulator. ( If i feed Complex input to a signal ADC(RX0). ADC core sample the data and then Complex NCO for IQ demodulator and followed by Decimator fo I and Q data samples)

7. Is NCO after or before ADC Core?

8. ADC RF port Impedance S-Parameter File



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[edited by: Manikandan_M_M at 3:41 PM (GMT -5) on 30 Dec 2023]
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  • Hello,

    Answer to your questions are as follows:
    1)  Isolation data exists but someone from factory will need to provide this information since it does not exist on product web page.

    2) The Rx input is fairly well behaved in the the region of 2.7 GHz as shown below.  One could also use a lower cost balun like the Mini-Circuits TCM1-83x for similar response as shown in UG1578.



    3) Noise Figure is considered under small signal conditions where ADC thermal noise typically dominates with ADC quantization noise having less of an impact. Based on frequency plots above.........the input power to reach the ADC's full-scale input power is similar at 2.7 GHz as it is at lower frequencies (give a few 1/10ths for ripple in passband response.  

    If we estimate the noise floor at -151 dBc/Hz at signal levels where jitter/phase noise does not contribute and a full-scale input power of 3.9 dBm (1.4 Vpk-pk into 100 ohm).........the noise figure is around 26.9 dB.  Note that datasheet provides typ spec of 26.8 dB. 


    4) Worst spurious within a "specified passband region" is highly dependent on how wide this region is and at what IF frequency.    Normally one tries to select IF regions that avoid the 2nd or 3rd harmonic from falling in this region.  The closest data shown in the datasheet is at 4 GSPS (vs 3.6 GSPS) at 2.7 GHz input.  In this particular case, the highlighted harmonic is an alised 2nd harmonic.   If the sample rate was reduced to 3.6 GSPS, the aliased harmonic would fall close to DC while the aliased 3rd harmonic would fall near center of Nyquist (900 Mhz).  Note that the HD2/HD3 levels can very between the different ADC's.




    5) Architecture 1 is preferred since it reduces number of ADC's required per RF channel.
    6) The desired signal falling around 2.7 GHz can be easily downconverted by the complex NCO/12x decimation filter .

    7)  The complex NCO is typically the 1st stage after the ADC .  It is worth noting  that an optional programmable FIR filter also exists between ADC core and complex NCO but would not be required in a narrowband Architecture 1 scenario where the passband region is quite low (i.e. IQ rate of 300 MSPS has usable passband of 240 MHz).

    8)  S parms are on product web page and can be downloaded.  Also suggest that one consider the RF models files that are more usefull in optimization than Sparms alone.



  • 2) As per UG-1578, The 4 GSPS ADC in the AD9081 consists of two sub ADCs operating at one half of the ADC sample rate with the sampling clocks adjusted to be near a 180° offset. Is this applies to AD9209 as well. If yes, I have to take care of Interleaving spur.(Fs/2). What is digital coupling spur(Fs+/- Fs/4)?

  • Hello,

    Yes the AD9209 is the Rx portion ONLY of the AD9081 and the ADC core consists of two sub-ADC's sampling at ideally 180 degree offsets.  The ADC core also includes on-chip active calibration/control loop that maintains  near 180 degrees sampling offset (as well as gain mismatch) to suppress the "image" spur (typically below -80 dBc) hence does not require further user calibration.  Note........the calibration loop requires user to specify the Nyquist zone as being odd or even (per API setting).  

    Since some of the core ADC core logic operates at FS/4........some amount of this clock energy does couple onto the the ADC sampling clocks resulting in a spurious images around  FS/4 +/-FIN as shown below with highlighted spurs attributed to this mechanism for FIN=2.7 GHz and FS=4 GSPS.  Note that this spur level is shown for one of the ADC's and can differ among the ADC's.



  • Is AD9209 is a 12-Bit or 16-bit ADC. As per datasheet, it is 12-bit ADC. But as user-guide, both N and NP are 16-bits

  • Hello,

    The ADC core itself is a 12-bits hence one gets 12-bit output when bypassing digital block.  If digital block is used to decimate the ADC output data, the digital block will provide 16-bit data instead since digital block is implemented with 16-bit truncation when performing math functions to implement filter structure.

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  • Hello,

    The ADC core itself is a 12-bits hence one gets 12-bit output when bypassing digital block.  If digital block is used to decimate the ADC output data, the digital block will provide 16-bit data instead since digital block is implemented with 16-bit truncation when performing math functions to implement filter structure.

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