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AD9273 Read chip ID using SPI

Category: Datasheet/Specs
Product Number: AD9273

Hi,

According to the AD9273 datasheet, all registers except Register 0x00, 0x02, 0x04, 0x05, and 0xFF are buffered with a master-slave latch and require writing to the transfer bit. I would like to read the chip ID from the register 0x01. This is a read-only register, but from the datasheet, it means that this register is also buffered with a master-slave latch.

Does this mean that I need to write to the DEVICE_UPDATE register at 0xFF first in order to read from the chip ID register at 0x01? Right now, I did not write to this DEVICE_UPDATE register. I am sure that I am sending the correct bits to read the chip ID, but I am not getting the correct results as expected and I am wondering if that is because I did not write to the DEVICE_UPDATE register first?

Thanks!

  • Hi YHZ123,

    A few things could be happening here. To start maybe you can check what SPI mode is used. 

    And then refer to AN877 for additional information.

  • Hi Arvs,

    Thank you for your reply. I tried to check something else. So as per the datasheet, the SDIO pin works with 1.8 V logic, although it can be made 3.3 V logic tolerant by inserting a series resistor, which I have inserted. I probed the SDIO pin of the ADC (pin 52) directly with my oscilloscope probe and I noticed a very weird voltage decay behaviour. Please refer to the attached document for the screenshot. 

    My FPGA is CMOD A7 from Digilent. The SDIO voltage from AD9273 for Logic 1 is 1.79 V, but V_IH of Artix-7 in LVCMOS33 IO Standard is 2 V minimum. So due to incompatible voltage levels, it makes sense that the FPGA will be outputting the incorrect digital values.

    So to recap, the SDIO pin from the ADC is supposed to output 1.8 V logic levels right? If yes, then it makes sense that the FPGA will read the 1.8 V logic levels incorrectly because my FPGA works with 3.3 V logic instead. Therefore, I should use an external voltage translator between my FPGA and ADC right?

    However, do you know why there is this weird voltage decay behaviour seen when I probe the ADC SDIO pin directly?

    Thank you.PDF