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AD9273 Read chip ID using SPI

Category: Datasheet/Specs
Product Number: AD9273


According to the AD9273 datasheet, all registers except Register 0x00, 0x02, 0x04, 0x05, and 0xFF are buffered with a master-slave latch and require writing to the transfer bit. I would like to read the chip ID from the register 0x01. This is a read-only register, but from the datasheet, it means that this register is also buffered with a master-slave latch.

Does this mean that I need to write to the DEVICE_UPDATE register at 0xFF first in order to read from the chip ID register at 0x01? Right now, I did not write to this DEVICE_UPDATE register. I am sure that I am sending the correct bits to read the chip ID, but I am not getting the correct results as expected and I am wondering if that is because I did not write to the DEVICE_UPDATE register first?


  • Hi,


    I would like to ask for a little more information to be able to help you better.


    Are you using the AD9273 and its eval board/kits and software?

    When trying to read the chip ID register, you stated that you are not getting the correct results. My question is, what are your readback results?

    Aside from the chip ID registers, did you try reading back other buffered registers as well?

    These registers should have default values that you can confirm. For example, the FLEX_GAIN register at ADDR 0x11 has a default value of 0x06.

    Have you tried reading the unbuffered registers as well? They should have default values too.

    Please let me know.




  • Hi Arvin,

    Thanks for your reply. 

    1. No, I am not using the Eval board and the software. I am using my own PCB and FPGA and my own Verilog code.

    2. When I read the chip ID register, my readback results are 0xF0, instead of 0x2F.

    3. Yes, I just tried to read from other buffered registers and un-buffered registers. However, I noticed something really strange. If the last bit of the address I am trying to read from is 1, then I will always readback 0xF0. For instance, if I read address 0x09, I get back 0xF0 and if I read address 0xFF, I also get back 0xF0.

    However, if the last bit of the address I am trying to read from is 0, then I will always read back 0x00. For instance, if I read address 0x04, then I will get back 0x00 and if I read address 0x10, then I also get back 0x00.

    4. So basically, there are only two types of data I can read back, which are 0xF0 or 0x00 and this is clearly wrong.

    5. At this point, I am really confused about what is happening. Any suggestions on what else I could try? There could be a hardware fault, i.e. maybe the ADC is burned but I am really not sure...

    Thanks in advance!

  • Hi YHZ123,

     Apologies for the delayed response.

    As Ashraf has stated, the DEVICE_UPDATE register is only needed when writing to the registers. This answers your first question.

    Based on your response to my initial queries, it seems you are encountering some SPI errors still. There can be a variety of reasons for this, like the clock frequency, alignment, actual connections, etc.

    Since you are not using the eval board and software, I cannot easily replicate your results.

    To be able to assist you better, maybe you can provide the following:

    • Schematic circuit, specific to the SPI connections of the AD9273 and the FPGA.
    • Oscilloscope shots of the SPI pins doing a read command of 1 buffered and 1 unbuffered register.




  • Hi Arvin,

    Thank you very much for your response and apologies for my delayed reply. I attach to this my schematic diagram, my FPGA Verilog code, and my oscilloscope screenshots for reading a buffered register (CHIP_ID, address is 0X01, default value is 0X2F) and a non-buffered register (CHIP_GRADE, address is 0X02, default value is XX10XXXX, I am using the 50 MSPS chip).

    As you can see, for the buffered register (CHIP_ID), I am reading back but the correct result should be 0x2F. For the non-buffered register (CHIP_GRADE), I am reading back but the correct result should be XX10XXXX.

    I really don't know what could be going wrong here. Any suggestions would be greatly appreciated, thanks!PDF

    `timescale 1ns / 1ps
    // Company: 
    // Engineer: 
    // Create Date: 13.11.2023 19:48:42
    // Design Name: 
    // Module Name: spi_readchipID_v1
    // Project Name: 
    // Target Devices: 
    // Tool Versions: 
    // Description: 
    // Dependencies: 
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    // improved version 25 nov 23, 土办法解决了。
    module spi_readchipID_v1(
        input reset,
        input clkin,
        output reg CSB,
        inout wire SDIO, // inout MUST be wire!
        output wire SCLK,
        output wire test_PMOD_CSB,
        output wire test_PMOD_SCLK,
        output wire test_PMOD_SDIO,
        output fiveV_levelshifter_EN
    	reg [4:0] count1;
        reg [4:0] count2=5'd0;
        reg [15:0] address_command = 16'b1000000000000001; // this is copied from datasheet
    	assign fiveV_levelshifter_EN = 1'b0; 
    	assign test_PMOD_CSB = CSB;
    	assign test_PMOD_SCLK = SCLK;
    	assign SDIO = (count2>=5'd0 && count2<=5'd15) ? address_command[15]:1'bz ;
    	assign test_PMOD_SDIO = SDIO;
    // generate 10 MHz SPI SCLK
    clk_wiz_0 instance_name_sclk_spi
        // Clock out ports
        .clk_out1(SCLK),     // output clk_out1
        // Status and control signals
        .reset(reset), // input reset
       // Clock in ports
        .clk_in1(clkin)      // input clk_in1
    // generate 200kHz CSB
     always @(negedge SCLK or posedge reset) begin
     if (reset) begin
     CSB <= 1;
     count1<= 5'd23;
     else if (count1 == 5'd0)
     CSB <= ~CSB;
     count1 <= 5'd23; //div 2(K+1) so this is div 50 from 10 MHz.
    always @(negedge SCLK or posedge reset) begin
    	if (reset) begin
    	address_command <= 16'b1000000000000001;
    	else if (count1 ==0 && CSB) begin
    	else if(count1 != 0 && !CSB) begin
    	address_command<= address_command << 1;
    	count2 <= count2 +1'b1;
    	else if (count1 != 0 && CSB) begin
    	address_command <= 16'b1000000000000001;
    	count2 <= 5'd0;
    	else if (count1==0 && !CSB) begin
    	address_command <= 16'b1000000000000001;
    	count2 <= 5'd0;

  • Hi, thought that I should add more details. I am giving the ADC a clock of 10 MHz for its sampling clock. The SPI SCLK is also running at 10 MHz. I am currently using the 50 MSPS model, but I want to work at a slower speed of 10 MHz instead for my application.


  • Hi YHZ123,

    Just one quick question/clarification:

    Have you tried reading register 0x00(CHIP_PORT_CONFIG)? I wanted to know whether the device is set to MSB-first of LSB-first.

    Based from your earlier responses(when address ends in "0", readback is always 0x00), your results are 0x00 also. Is this correct?

  • Hi Arvs,

    Thank you for your reply. I did not touch the 0x00 (CHIP_PORT_CONFIG) register at all, so it should still be in the default mode which is MSB first.

    Yes, if the address ends in 0, I always readback 0x00.

  • Hi Arvin,

    Happy New Year! Any ideas how I can fix my bug? Thanks!

  • Hi YHZ123,

    A few things could be happening here. To start maybe you can check what SPI mode is used. 

    And then refer to AN877 for additional information.

Reply Children
  • Hi Arvs,

    Thank you for your reply. I tried to check something else. So as per the datasheet, the SDIO pin works with 1.8 V logic, although it can be made 3.3 V logic tolerant by inserting a series resistor, which I have inserted. I probed the SDIO pin of the ADC (pin 52) directly with my oscilloscope probe and I noticed a very weird voltage decay behaviour. Please refer to the attached document for the screenshot. 

    My FPGA is CMOD A7 from Digilent. The SDIO voltage from AD9273 for Logic 1 is 1.79 V, but V_IH of Artix-7 in LVCMOS33 IO Standard is 2 V minimum. So due to incompatible voltage levels, it makes sense that the FPGA will be outputting the incorrect digital values.

    So to recap, the SDIO pin from the ADC is supposed to output 1.8 V logic levels right? If yes, then it makes sense that the FPGA will read the 1.8 V logic levels incorrectly because my FPGA works with 3.3 V logic instead. Therefore, I should use an external voltage translator between my FPGA and ADC right?

    However, do you know why there is this weird voltage decay behaviour seen when I probe the ADC SDIO pin directly?

    Thank you.PDF