I have a FPGA evaluation board, HSC-ADC-EVALEZ. I also have an evaluation board AD9684-500EBZ connected to the FPGA board.
I can capture the data from the I-Q demodulator using MATLAB codes.
I have two differential input channels and need 12 to 14 bits of resolution.
The sampling rate of AD9684-500EBZ is too high for my application. I need sampling rates of 1- 500KSPS, 2- 1000 KSPS, and 3- 4000 KSPS.
What ADC chip (and its evaluation board) do you suggest for my application?
Do we have any chip with external clock frequencies of, let’s say, 100KHz to 20 MHz to get sampling rates of from below 500 KSPS to around 20 MSPS or so?
With AD9684-500EBZ, I get an error when I reduce the external clock frequency below 94 MHz, so I cannot capture data at speeds lower than 94 MHz. The datasheet says the minimum clock frequency is 300 MHz, but it works as low as 94 MHz.
Any help is highly appreciated.
Thank you,
Iraj
