Can AD-9680 synchronize channel A and channel B?

Hi Naruto0916 

Thanks for your interest in AD9680.

Channel A and Channel B is time aligned, but the Channel B has a 180-degree phase shift from Channel A.

This is due to the Balun output at the Analog Input. It is swapped to keep the two channels as symmetric as possible, without adding vias as such.

Regards,

Adrian

Hi Adrian

Thank you for your reply.

If set the "output data length" in VisualAnalog as 1048576, the channel A & B data will have synchronization issue like below picture.

Another question is we try to set the "output data length" in VisualAnalog as 524288 and the result seems synchronous.

We are not sure the PC that operate VisualAnalog will impact data length 1048576 synchronization issue??

Do we need use more powerful pc to operate VisualAnalog?? Or have any suggestion to help to fix synchronization issue in 1048576 data length??

Currently, our pc's hardware is: intel i5 cpu, 16g ddr ram, & 1G SSD.

Our test environment is like below picture:

Cheers

Naruto

Hi Naruto0916 

We recommend using other data length settings other than 1048576. If you still want to proceed with 1048576 or above data length per channel, you need to create a custom FPGA program file that uses the external SDRAM as memory.

Regards,

Adrian

Hi Adrian

Thank you for your reply.

1.

Is it the limitation of  VisualAnalog or AD9680BCPZ-500 / ADS7-V2's limitation??

We saw the data from wiki (https://wiki.analog.com/resources/eval/ad9680-1000ebz) and it mention:

The ADs7-V2 FPGA software supports up to 2M FFT capture (1M per channel).

Have more detail information let us know what happen and cause we can't use 1048576 or above data length??

2.

Can you explain more detail about "uses the external SDRAM as memory"??

As we know, the ADS7-V2 have 8G ddr ram on board. Do we need use the ddr ram as memory??

3.

Have sample code or document about " create a custom FPGA program file"??

We have no idea how to do it.

Cheers

Naruto

Hi Adrian

Data lengths of 1048576, 2097152, 4194304 and 8388608 are built-in feature of AD9680 software.

You even illustrated the capture of these data lengths in your prior answer.

We acquired the AD9680 board & SW with the intend to do this - long data lengths sampling.

From my perspective, the AD9680 board/SW has a bug!!!

You mentioned the need for different FPGA image and use of external memory.

Well, we have struggled on this issue for weeks. Please help us rectify the bug!

We wish to know how to let long data length setting work like your above pictures as soon as possible.

Can you also tell us the hardware spec. of your pc to operate VisualAnalog??

We may reference it to upgrade our pc to operate VisualAnalog.

Thank you.

Cheers

Naruto 

Hi Naruto0916 

The current available FPGA program file at the Visual Analog software uses the internal memory (BRAM) of the FPGA with data length less than or equal to 1048576 samples per channel while the external DDR memory (SDRAM) is used when the data length is higher than that.

You can verify if the SDRAM is enabled using the SPI Controller software, load the config (File > Cfg Open) ADFPGAspiR03.cfg. Read register address 0x0142, if bit[0] = 0 (BRAM is being used) while bit[0] = 1 (SDRAM is being used).

Regards,

Adrian

Hi Adrian

Thank you for your reply, we will try this way.

And about the hardware spec. of the pc that operate VisualAnalog, have any suggestion??

We try the 8388608 data length in our testing and the pc become slow.

Currently, our pc is intel i5 and 16G ddr ram.

Do we need more ram or intel i7 cpu??

Thanks and have a nice weekend.

Cheers

Naruto

Hi Naruto0916 

On my evaluation, having a data length of 8388608 per channel will take about 20 to 30 seconds wait time for the output in Visual Analog with an i7 12th gen. 10-cores CPU. While with an i5 6th gen. 2-cores CPU took about 1.5 to 2 minutes to produce the output, with both CPUs having the same 16GB RAM.

Additional CPU cores will help to reduce the wait time for the Visual Analog output.

Regards,

Adrian

Hi Adrian

We try to enable the SDRAM using the SPI Controller software by your suggestion and verify the output data length more than 1M.

And a stranger thing is the result of data length 2M, 4M, and 8M. All data of these 3 data length is synchronous.

But, the channel A and B data of 1M(1048576) data length setting still has synchronization issue.

From the waveform analysis of VisualAnalog, the lines of channel A and B still can't overlap if we set the output data length as 1M.

Have any suggestion about 1M data length synchronization issue??

Cheers

Naruto

Hi Adrian

We try to enable the SDRAM using the SPI Controller software by your suggestion and verify the output data length more than 1M.

And a stranger thing is the result of data length 2M, 4M, and 8M. All data of these 3 data length is synchronous.

But, the channel A and B data of 1M(1048576) data length setting still has synchronization issue.

From the waveform analysis of VisualAnalog, the lines of channel A and B still can't overlap if we set the output data length as 1M.

Have any suggestion about 1M data length synchronization issue?? Or we got a broken AD9680BCPZ-500 / ADS7-V2 ??

Allow me to explain this more clearly -
The AD9680 channels are at 180-phase relative to each other as you previously mentioned.
We adjust the SMU200A (signal source) to generate 180-phased signals out of its channels A and B as inputs to AD9680.
With Data Length of 2M, 4M and 8M, the AD9680 time-sampled data of the 2 channels are synchronous and can be plotted to visually see overlapping graphs.
We observed the following issues:
1. However in the case of 1M data length the 2 channels were not synchronous or overlapping.
2. The 2M, 4M and 8M data appears to have truncated/dropped some section of the sampled data. When we decode the OFDM communication signal, we found gaps in the resulting packet stream. Also, when the time-sample data of the 2 channels were plotted we saw incomplete OFDM signal (like a chunk of the modulation was dropped and a short remnant section was left behind)

Cheers

Naruto