AD9208 has a small signal at FS/4 and the small signal amplitude will change when resetting the JESD bus.

Hi summersuny,

Could you provide a screenshot of your measurement? What's the spurs level at fs/4. Typically, it is expected to observe such spurs lower than -100dBFs.

Based on your register settings:
1, I have noticed that your JESD settings should be: L = 8, F = 2, M = 4.
2, No need to set register 0x327/0x347 for normal operation.
3, Register 0x0311 and 0x331 are both set to 0x05, only channel B data was selected.
4, It's recommended to write 0x0571 0x14 before 0x1228

Regards,

Alvin

Dear alvin_meng ,

Thank you for your reply.

1.Really， L = 8, F = 2, M = 4.

2.Accept your suggestion.

3.Only channel B data was selected 4.

4.Accept your suggestion.

0x0571 0x15
0x058E 0x03
0x058F 0x8F
0x058B 0x07
0x058C 0x01

0x0571 0x14
0x1228 0x4F
0x1228 0x0F
0x1222 0x00
0x1222 0x04
0x1222 0x00
0x1262 0x08
0x1262 0x00

FFT points 262144. The spurs level at first was 101 and the latter was 109.

Maximum level is 198.

Why the two collected data are inconsistent. What can I do to reduce or eliminate the spurs.Thank you very much.

Hi Summersuny,

Was this data collected on the evaluation board or on your own board?

If you see the datasheet, you could also find the spur in the red circle.

Could you provide your raw samples?  Let me check if the spur is still within the specification, and it's not introduced by data processing or something else.

Could you try the 1DDC setting with L = 8, F = 2, M = 2 to see if the spur is still there?

Regards,

Alvin

Hi alvin_meng,

1.The data collected on my own board.

2.I hace tried the 1DDC setting with L = 8, F = 2, M = 2 and the spur is still there.Sometimes it is big but sometimes small on same board.

I don't konw how to upload  raw samples.Can you tell me how to do?

Thank you.

Hi Summersuny,

Could you email the raw data to alvin.meng@analog.com.

The DDC output is 16-bit data stream, could you confirm your FFT analysis was using 16bit resolution or 14-bit?

Regards,

Alvin

Hi alvin_meng, 

My FFT analysis is using 16bit resolution and I have emailed you.

Thanks

Thanks Summersuny,

I will check my email and get back to you later.

Regards,

Alvin

Thanks Summersuny,

I will check my email and get back to you later.

Regards,

Alvin

Hi Summersuny,

I've got your raw sample data and here is the worst case FFT plot. The spurs level is about -98dBFs, it's already very small , this should be coupled outside of the ADC, seems to be from FPGA reference clock coupling(375M) and its HD2(750M), as your data was using 1 DDC configuration, reference clock to FPGA is 375M. 

You could check this by shorting the analog input AinP and AinN, if there's no such spur, this can prove that the spur is not from analog input or internal crosstalk of the chip. 

You could check your PCB to see if you could find the coupling path on your board.   Please let me know if you have any findings on your board.

Regards,

Alvin

Hi alvin_meng,
I have shorted the analog inputs AinP and AinN and there is the spur as before.If Jesd is reset, the the spur will change and sometimes big ,sometimes small.
FPGA reference clock is 96.77MHz. The reference clock(qpll0_refclk) is generated by the FPGA MMCM.The input of MMCM is 96.77MHz and output is 187.5MHz.
The clock provided to the FPGA in the hardware is 96.77MHz.

Is there this spur on the evaluation board?
This is my schematic diagram. Please help to see if there are any problems.

Thanks

Hi Summersuny，

This may be coupled from PCB, your schematic should be fine. 

As our earlier discussion （please see the test plots I attached）, on evaluation board with default hardware setting, you could also see similar spur at fs/4. The spurs level is around -103dBFs, may be change a little with different captures vs time.

I checked my earlier note about the setup several years ago, I connected two 50ohm load at the SMA port and change the hardware setting to DC coupling for analog input.

The changes please refer to below screenshot:

Here's the FFT plot that I captured after hardware changing, as you can see there's no such spur at fs/4. This can prove the spur is coupled from outside of the chip, but it's already very low, I didn't spend time to investigate it. Your experiment could also see 375M and 187.5M spurs, as you're using lower reference clock to FPGA.  If your system has very strict requirement for spur performance, you could try adding a metal mask for ADC in your new design to see if it improves the spurs. but for current stage, I think it's very difficult to improve it because this seems to be a hardware related issue.

Hope it helps.

Regards,

Alvin