I am working in a complex board, in which we capture up to 12 signals (simultaneously) with up to 6 units of the MAX11190 (dual ADC).
A companion board is triggering the start of the acquisition (FLAG), which is converted to trigger low the CS* of the 6 converters in parallel. Then a high speed controller receives the 12 lane SPI DOUT signals (2 DOUTs per ADC). So far so good.
We have studied the datasheet and concluded that cannot afford to put the chip in low power mode between acquisitions. We have to respond promptly to the external FLAG signal, cannot afford a dummy conversion to wake up the ADC.
My question is: can I switch off the SCLK signal between acquisitions in order to reduce the overall power consumption? I cannot find in the datasheet any indication about whether the SCLK can be stopped between acquisitions. AFAIK there are converters in which I can stop the SCLK but others require a non-stopping clock.
I can (by firmware) stop the clock, watch for the external FLAG signal, then start the clock and drive the CS* signals of the ADCs in order to properly start the acquisition. Then, at the end of the conversion, having received all the serial data, switch off again the SCLK (high state). Is this a valid mode of operation?