The hardware board of the ADC and FPGA of the jesd204b interface enables high-speed ADC data acquisition inside the FPGA by calling the jesd204b IP core.
During debugging JESD204B:
The configured operating modes are L = 4, M = 16, F = 6, S = 1, N' = 12, K = 32;
Clock configuration: lane_rate = 3GHz, core_clk = 75MHz, refclk = 150MHz, sysref = 9.375MHz;
The waveform plot is as follows:
Subclass 0 and subclass 1 modes can receive K codes, but sync does not pull high;
There is no problem pulling the sync pin directly with the FPGA;
Another case is that after I load the FPGA program, I configure the clock to the external clock chip, then reload the program, and then configure the AD chip, at which point the K code is detected, and the SYNC signal can be pulled high.
I would like to ask everyone, what is the reason for this? Thank.