Designing with AD9625 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter

Hi joniengr081 

Thanks for your interest in AD9625.

Your query is acknowledged and will be responded by the product owner soon.

Regards,

Adrian

Hi,

We have some reference designs which contain AD9625, for example fmcadc2 (with VC707 and ZC706), fmcadc5 (with VC707), fmcomms11 (with ZC706).

Take a look at these, maybe they would be of use, and let me know what do you think.

Best regards,
Iulia

Hi joniengr081 ,

Do any of the suggested reference designs help you?

Regards,
Iulia

Many thanks for your consideration and reply.

You mentioned reference designs available to interface AD9625 with VC707 and ZC706.

Which I/Os on FPGA side we can use to interface AD9625 ? There are I/O Banks in Xilinx FPGAs which are described as HP I/O Bank and HR I/O Bank. But I know that they support up to 1.2 Gbps differential signals. 

I guess the serial GTH (Giga bit serial transceivers) have been used in the reference designs for VC707 and ZC706. Can you please check and confirm ? 

The other questions I have is related to board design.

Any suggestion on PCB stackup layers which is preferred ? 

Any suggestion on dielectric to be used in PCB ?

Can we use FR4 as dielectric in PCB stackup ? 

Any suggestion on PCB layout and routing ?  

One more question, I see that there are eight lanes at the output, SERDOUT[0]± to SERDOUT[7]±. What is the data rate on each lane ? for each sampling rata 2.6 GSPS / 2.5 GSPS / 2.0 GSPS. 

Hi,

The projects I have listed, they use JESD204B which needs GTH transceivers.

Regarding the FPGA questions, maybe it would work with an Zynq UltraScale+, but I'm not sure of all your requirements so you should check.

About the board design, the FPGA reference design forum can't help you, and that's why I will move this to the High-Speed ADCs forum which deal with this.

Best regards,
Iulia

Hi, Thanks for your reply. We will consider high speed serial links, GTH in ZYNQ UltraScale+. 

But what about the data output rate on eight lanes SERDOUT[0]± to SERDOUT[7]±. What is the data rate on each lane ? for each sampling rata 2.6 GSPS / 2.5 GSPS / 2.0 GSPS in AD9625 ?