Category: Hardware
Product Number: AD9695
Hello,
We're going to use AD9695 to implement a high performance ADC system. When we browsed the datasheet, we observed that at p.6 the SFDR of the ADC doesn't monotonically decrease with frequency.
It increases from 340MHz to 750MHz and again from 1400MHz to 1700MHz. I'm really a newbie in ADC but I know that in analog buffer design, the lineariity usually gets worse when operated in higher frequency. Could somebody tell me the potential reason causing this? Thanks.
Edit Notes
Add a picture.[edited by: jamesjjc at 5:36 PM (GMT -4) on 15 Aug 2023]
