AD9257 sync function

Question

Hi, Engineers of AD9257, 
 
 I am using two pcs AD9257 in my board, and their clock reference come from the same 40MHz clk on board, but sampling rate is 20MHz, So I enabled the clock divider 2. the sync pin of two AD9257 connect together and from GPIO of FPGA. 
 I found the datasheet says below: 
 "Input Clock Divider the AD9257 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The AD9257 clock divider can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling." 
 I noticed the defaults value of Register 0x109 is 0x00, If I want to synchronize two pcs AD9257, Should I set both Bit0 and Bit1 to 1? If so, after I set them, the two pcs AD9257 will synchronize after the sync posedge output from my FPGA? 
 
 One more question, after the two pcs AD9257 synchronized, will the dco clock phase of the two pcs AD9257 be same? Because I need use the ADC sampling datas to beamform. 
 Thank you in advance, 
 Okwonjo.

JAlipio · Accepted Answer

Hi Okwonjo, 
 Thanks for your interest in AD9257. 
 If you wanted to use the clock frequency divider to divide the applied clock frequency by 2, for two AD9257s you would do the following for both AD9257 devices: 
 Write Register 0x0B = 0x01 #set clock divider to divide-by-2 Now the frequency of the clock applied to the CLK+/- pins will be divided by 2. If you applied a 40MHz clock to CLK+/-, then both AD9257s will sample at 40MHz/2 = 20MHz. 
 If you want to synchronize both AD9257s, then: Write Register 0x109 = 0x01 #enable SYNC mode Apply a pulse to the SYNC pins of both AD9257 devices, satisfying the setup and hold time requirements with respect to the clock signal, as shown in Table 5 and Figure 4 of the AD9257 datasheet.

Now the clock dividers will be reset to the same state every time there is a SYNC pulse, so each AD9257 will receive the same sampling edge of the internally divided clock. The same clock signal and same SYNC signal must be applied to both AD9257 devices for them to be synchronized. Make sure to have the same path length for the clock and SYNC signal. 
 I f you are not using the AD9257 clock frequency divider (Register 0x0B = 0, which is default value resulting in divide-by-1), then multiple AD9257s will automatically be synchronized if they all receive the same sampling clock. The SYNC pin is not needed in this case. 
 The two AD9257 should have the same DCO clock phase, since the SYNC is enabled. 
 Regards, 
 Adrian)

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AD9257 sync function