Hi, Engineers of AD9257,
I am using two pcs AD9257 in my board, and their clock reference come from the same 40MHz clk on board, but sampling rate is 20MHz, So I enabled the clock divider 2. the sync pin of two AD9257 connect together and from GPIO of FPGA.
I found the datasheet says below:
"Input Clock Divider the AD9257 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The AD9257 clock divider can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling."
I noticed the defaults value of Register 0x109 is 0x00, If I want to synchronize two pcs AD9257, Should I set both Bit0 and Bit1 to 1? If so, after I set them, the two pcs AD9257 will synchronize after the sync posedge output from my FPGA?
One more question, after the two pcs AD9257 synchronized, will the dco clock phase of the two pcs AD9257 be same? Because I need use the ADC sampling datas to beamform.
Thank you in advance,