Improving ADC reading stability

Question

I currently use this AD9226 ADC Acquisition Analog To Digital Converter FPGA Development board, which uses AD9226 ADC and AD8138 Differential Driver. I fed the digital output to an FPGA. Also, the CLK signal for the ADC is generated by the FPGA. 
 
 Now, when measuring a constant voltage, the measurements I get are as shown in the image below. 
 
 We could see that the readings consist of a couple of lines, where each line has a 1-bit difference to its adjacent "ine. Even though the measured voltage is a constant DC, the readings jump around these couple of lines. 
 How can I improve reading stability? It doesn't necessarily have to be only one line, but at least I could reduce the number of lines for a DC voltage measurement. Thank you.

FormerMember · Accepted Answer

Hello,

The code distribution that is shown in plot is a result of thermal noise from the input signal source, the AD8138 amplifier and the AD9226. By removing the input source and shorting the input.........one can determine how much contribution is from the combined AD8138/AD9226 by collecting a large sample population, plotting its histogram, and determining the rms code level of the dataset. If it is lower than the rms level when a DC voltage is applied to the input.......than the input may be a major source of the noise.

To improve the variation of code due to noise..............one can filter the data coming from the AD9226. The simplest filter is just a running averaging number of samples. The more samples averaged........the more stable the reading will be over time.

Partner Forums

Partner Libraries

Products Mentioned

Improving ADC reading stability