AD9689: Does the decimation filter cause a DC component?

Hi y_suzuki,

We have many great articles that talk about how DDC works.

I recommend that you read these articles first to have an overall understanding about DDC.

What’s Up With Digital Downconverters—Part 1 | Analog Devices

What’s Up With Digital Downconverters Part 2 | Analog Devices

For the second question. DDC does not produce any DC components as you can see in blow measurement plot with DDC.

If customer board has DC related problem, please provide more details, so we can have further discussion about it.

Regards,

Alvin

Hello Alvin,

I appreciate your support.
Just I'm reading the documents which you mentioned.

If the resolution affects quantum error, I think HB4 will contribute to it mostly because HB4 consists of 15-bit coefficients.
Could you please show me the spectrum using a decimation rate of 16 or 40? The configuration of the decimation rate of these includes HB4.

Best regards,

y_suzuki

Hello Alvin,

The customer asked us the following additional question.

1. How much dynamic range (bit width) is used in the calculation, and at which bit is the rounding process performed in the calculation process?
2. Is the rounding process "rounding off", "rounding down" or "rounding up"?
3. Is the rounding process used for the final 14 bits "rounding"?

Could you give me the answer in your possible?

Best regards,

y_suzuki

Hi y_suzuki，

The bit growth is a little bit complex to discuss here, it depends on the actual coefficient values.
Customer could load our coefficient values of the HB filters in the datasheet using MATLAB to obtain the real response after filtering processing easily.

There're two 14-bit ADC cores running within AD9689. The DDCs output a 16-bit stream(even though the analog core only outputs 14 bits).
The screenshot above is 16-bit FFT plot with HB1 enabled only. I also captured HB4+HB3+HB2+HB1 configuration as below for your reference.

Regards,

Alvin

Hello Alvin,

> There're two 14-bit ADC cores running within AD9689. The DDCs output a 16-bit stream(even though the analog core only outputs 14 bits).

Does the conversion truncate the LSB 2Bit from 16Bit to 14Bti at the DDC output?


> The screenshot above is 16-bit FFT plot with HB1 enabled only. I also captured HB4+HB3+HB2+HB1 configuration as below for your reference.

Thank you for the confirmation.
I can see no DC component.

Best regards,

y_suzuki

Hi yz-suzuki,

Does the conversion truncate the LSB 2Bit from 16Bit to 14Bti at the DDC output?

--No, as discussed earlier, the DDC output is 16-bit width, please refer to figure 109 in the datasheet.

The AD9689 has two ADC channels and four DDC channels, each DDC channel has two input ports which support to select data from ADC A or ADC B. It means the input of DDC from ADC core is 14-bit, and the DDC output is 16-bit, the converter number of bits, N, is set to a default value of 16.

Regards,

Alvin

Hello Alvin,

Thank you for your quick response.

> It means the input of DDC from ADC core is 14-bit, and the DDC output is 16-bit, the converter number of bits, N, is set to a default value of 16.

I could understand the resolution of the DDC output. I assumed the resolution of the JESD204B interface input is 14Bit but it allows 16Bit. This means the user can select the method of rounding.
Is the above FFT spectrum, that you presented, processed by 16Bit (No rounding)?

Best regards,

y_suzuki

Hi y_suzuki,

Yes, the plots that I attached are both 16-bit data from DDC out.

Regards,

Alvin

Hi y_suzuki,

Please try this method to see if it works.

1, click the 'Proceed to Memory Map' to the register memory view.

2, Nevigate to register 0x58F, and set 0x58F to 0xD, then click 'Apply selected'.

3, Proceed to Analysis, 

If you export the raw data, the 2 LSBs should be always ‘0'.

Regards,

Alvin

Hello Alvin,

I'm sorry, it was my mistake.
I confirm the exported data file, which I set "N" to 14Bit, and I found the 2LSB data is "00"  

Best regards,

y_suzuki