HardWare:Design with reference to official schematic diagram.
SoftWare:FPGA based on Xilinx:V7
Sample Rate:2.4G
JESD204B Link Completed OK;
JESD204B constant :F=1,M=1,L=8,N=14,N’=16,K=32;
We didn't supply the any signal to Board, and collected the noise directly. The tool we used was HIGH SPEED DATA CONVETER Pro,but the Noise Level was around -60 showed by tool, which should be around -80 normally(follows picture).
We have tried to configure various registers on FPGA and The principle design of hardware is checked.There is no improvement in the result.So I hope your engineer can give me five to solve this question.
could you give us some suggestion to debug this board .