We are facing unstable data capture situation with ADC AD9213. We are using four AD9213 ADC with Xilinx Kintex Ultrascale+ FPGA (XCKU15P). The Xilinx JESD204 v7.2 IP core is used (bought license used).
Sampling clock - 8GHz (generated from a RF signal generator)
Subclass 0, LR=10Gbps, L=12, M=1, F=1, S=8, HD=1, N=12, N'=12, CS=0, K=32
ADC1 => 12 GTY transceiver
ADC2, ADC3, ADC4 => 12 GTH transceiver each
The desired test pattern generation on AD9213 is set using SPI communication.
when we just power-on the board and provide the ADC sampling clock from the signal generator, the rx_tvalid signal doessn't go high. And the rx_sync signal changes to high and low continuously (not constant, it is trying to achieve the link)
The ADC1 works well, valid test pattern data received and the JESD204B IP core asserted the rx_tvalid signal (rx_tvalid on FPGA) high only under the following circumstances.
1. When we touch the ADC sampling clock input at the ADC side with a 50ohm RF cable. (rx_sync and rx_tvalid high)
2. When turn OFF and turn ON the signal generator output (50% of the time it causes the rx_sync and rx_tvalid high signals to go high,not always)
The ADC2, ADC3 and ADC4 never work even under the above-mentioned conditions.
What could be the cause of this phenomenon? How can we solve this issue?
Any help and guidelines will be great.