UNSTABLE AD9213 and JESD204B DATA CAPTURE

Hi pushpa94,

Thanks for your interest in AD9213.

Your query is acknowledged and will be responded by the product owner soon.

Regards,

Xavier

Hi Xavier!

Thank you for the response. I hope they reply soon.

Best regards,

Pushpa

Hi Pushpa,

Thank you for using the AD9213.

Unfortunately our FPGA experts are unavailable at the moment, so I'll ask some basic questions in the meantime (Sorry, I do not know about FPGAs).

• What is the difference between the GTY and GTH transceivers?
  • Are they both able to support the 10Gbps lane rate?
  • Are the reference clock requirements the same for both GTY and GTH?
  • Are the voltage levels and loading the same for GTY and GTH?
  • Is the same Xilinx JESD IP used for the different transceivers?
• Please make sure that your FPGA reference clock is synchronized to your ADC clock signal generator.
• Again, I'm sorry I don't know about FPGAs.

Also, are all the AD9213s being brought-up identically?

Thank you.

Doug

Hi DougI ,

Thank you for your answer.

What is the difference between the GTY and GTH transceivers?
    The main difference is that GTY can support high data rate whereas GTH transceivers data rate is limited.

Are they both able to support the 10Gbps lane rate?

   The attached pictures are from xilinx kintex ultrascale plus data sheet. Our FPGA speed grade is -2, even the lowest one -1 supports 10.3125Gbps on GTH transceiver.

docs.xilinx.com/.../ds922-kintex-ultrascale-plus (pg.45 & pg.54)
 
Are the reference clock requirements the same for both GTY and GTH?
Are the voltage levels and loading the same for GTY and GTH?
   yeah, I think so. Reference clock requirements is also same for both GTY and GTH.

Is the same Xilinx JESD IP used for the different transceivers?

    yes, same IP is used.

Please make sure that your FPGA reference clock is synchronized to your ADC clock signal generator.
    we have checked it for ADC1, it is synchronized. We will check for other ADCs as well even though the clock structure is same.

Again, I'm sorry I don't know about FPGAs.
   That's okay. Thank you for the help.

Also, are all the AD9213s being brought-up identically?
    We control the PWDN pin of the ADC individually. So, each ADC is powered on at different time.

Recently, I have observed the following behaviour on ADC1(GTY).

I perform the ADC startup sequence as mentioned in the AD9213 data sheet (pg. 108).
After performing the startup sequence, I assert the PWDN pin high for about 100ms, and then make it low.
(This case makes the ADC work well about 80% of the time, without touching the ADC sampling clock part at the ADC side).
Can you please analyse the cause of this as well? or is it reasonable to function like that?


Thank you for your help again.
Best regard,
Pushpa

Hi Pushpa,

You mentioned an RF signal generator produces your ADC clock. What clock signal power are you using and how are you converting the single ended clock to differential on your board?

Thank you.

Doug

Hi Dougl,
I am going to reply instead of Pushpa.

The clock signal power out of an RF signal generator is -10dBm. But, the signal power is reduced after some components such as balun, clock divider and etc. So, the differential Vpp of the signal at the clock input port of the AD9213 is 350mV.

We used a balun, BAL-0416SMG, to convert the single-ended clock to a differential clock.

Hi Dougl,
I am going to reply instead of Pushpa.

The clock signal power out of an RF signal generator is -10dBm. But, the signal power is reduced after some components such as balun, clock divider and etc. So, the differential Vpp of the signal at the clock input port of the AD9213 is 350mV.

We used a balun, BAL-0416SMG, to convert the single-ended clock to a differential clock.

Hi Dougl,
As Pushpa mentioned earlier, I'm using AD9213-10 for ADC and XCKU150-2FFVA1760 for FPGA.
The data transmission method is JESD204B, and 12 lanes are used.
It receives 8GHz input using an external RF signal generator, divides 8GHz into ADC clock and 250MHz into 8GHz, and provides refclk and core clk to FPGA. Therefore, phase synchronization is correct.
The problem is that the FPGA cannot read data from the ADC when it is first started, but if the RF output of the RF signal generator is turned on and off repeatedly, the FPGA starts to read the data.
What could be the cause of this phenomenon?
The strength of the RF signal generator signal and the input method to the ADC are the same as the previously mentioned methods.

Then, by inputting a reference analog signal to the ADC using another RF signal generator and checking the result value of the ADC while changing the frequency of the signal, the frequencies corresponding to the division ratio of the sampling frequency 8GHz, 4GHz, 2GHz, At 1 GHz, 500 MHz, and 250 MHz, the waveform is AD-converted normally, but at other frequencies, the waveform may be distorted. (Please see the attached pictures below)

These symptoms are sometimes output normally when the clock signal of the RF signal generator is turned on and off repeatedly.
What could be the cause of this phenomenon?

Also, we are using 4 AD9213s.
The ADC of Channel 1 uses the GTY port of the FPGA, and the ADC of the remaining 3 channels uses the GTH port of the FPGA.
The ADC using the GTY port shows the same symptoms as described above, but the other 3 ADCs using the GTH port cannot read data.
Is there any difference between using GTH port and GTY port?
Also, for ADCs using the GTY port, the FPGA outputs the SYNCINB signal as High, but for the ADCs using the GTH port, the FPGA outputs the signal as Low.
The frequency of Lane used for JESD204B is 10GHz.

If it is a problem with the frequency of the lane used for JESD204B, is it meaningful to test by lowering the frequency of JESD204B communication?

And ADC is using subclass 0 mode.
I understand that this mode doesn't require the use of sysref and trig inputs, is that correct?
Also, is the subclass 0 mode suitable for implementing a high-speed ADC with a sampling frequency of 8 GHz?

Thank you for your help.
Best regard,
Jo

Hi Josc,

I apologize for the very late reply.

I'd like to go back to the clock question. If the clock is not right then I think there is no use in trying to debug the other aspects.

It seems to me that -10dBm at the signal generator is too low. Even with no loss -10dBm into 106Ω is about 290mVpp_diff if I did my arithmetic correctly. This is too low for AD9213. With other elements in the clock path the signal making it to the AD9213 will be even lower.

Pushpa mentioned that touching the ADC clock sometimes made a difference. This is consistent with the clock being marginal.

Do you have the ability to increase the clock power?

Thank you.

Doug