ad9266 requirement CLK for working

Hi seokjaecho,

Thanks for your interest in AD9266.

The clock should be differential with 0.9V common-mode voltage per CLK pin with differential input voltage of 3.4Vpp as per datasheet. I suggest to probe the signals in the CLK+/- pins to check using an oscilloscope.

Figure 30 of the datasheet also depicts the internal clocking circuit of AD9266.

As guidance, I do not recommend using a clock source directly from FPGA since this will severely affect the AC performance of the ADC.

Regards,

Xavier

Hi seokjaecho,

Thanks for your interest in AD9266.

The clock should be differential with 0.9V common-mode voltage per CLK pin with differential input voltage of 3.4Vpp as per datasheet. I suggest to probe the signals in the CLK+/- pins to check using an oscilloscope.

Figure 30 of the datasheet also depicts the internal clocking circuit of AD9266.

As guidance, I do not recommend using a clock source directly from FPGA since this will severely affect the AC performance of the ADC.

Regards,

Xavier