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ad9266 requirement CLK for working

Category: Hardware
Product Number: AD9266

hello, I designed hardware using AD9266

i made clock for AD9266 on fpga, LVCMOS 1.8v.

i expected range of the clock has 0 ~ 1.8v, but when i observed 1.68 ~ 1.9v on clk 

however when i read on datasheet, if the clock has middle value 1.8v, work fine but ADC dosen't work

Can i get a exact vlaue about range of clock voltage?

best regards 

modifiy sentence mean
[edited by: seokjaecho at 2:19 AM (GMT -4) on 31 Mar 2023]
  • Hi seokjaecho,

    Thanks for your interest in AD9266.

    The clock should be differential with 0.9V common-mode voltage per CLK pin with differential input voltage of 3.4Vpp as per datasheet. I suggest to probe the signals in the CLK+/- pins to check using an oscilloscope.

    Figure 30 of the datasheet also depicts the internal clocking circuit of AD9266.

    As guidance, I do not recommend using a clock source directly from FPGA since this will severely affect the AC performance of the ADC.