Hi,
I'm using Xilinx FPGA (UltraScale XCKU040) to drive AD9689, and trying to read sampled data from JESD204B interface, but I encountered a problem:
I configured the following parameters for the AD9689-JESD204B interface:
L=8, M=2, F=1, N=14, N'=16, CS=0, T=2, K=32 (full bandwidth mode), so AXI-Stream will have 256 bits of valid data each time ,
My question is, according to what rules should I parse out the real sampled data from the 256-bit received data?
For example:
core0_sample0={rx_tdata[103:96], rx_tdata[71:66] };
...
core0_sample7=?
core1_sample0=?
...
core1_sample7=?
I also read Xilinx-pg066, but it's not very well described, I'm even more confused! !
Before that, I based on the configuration on the network: I tried to read the data, obviously it didn't work properly in test mode:
its data in ad9208_datab1 datab2 datab5 datab7 is always different from others(The data in red is shown)
So, can you tell me what rules should be used to parse out the real sampled data? Or where there is information or application notes or docs on this
I will be very grateful!
Regards,
Kyle
