Hi ADI Team,
We raised the same question in this thread: https://ez.analog.com/microcontroller-no-os-drivers/f/q-a/567828/ad9467-fmc-start-capturing-data-and-see-the-output-waveform-in-adi-iio-oscilloscope.We started a new thread because the one that was already started was not pertinent to the issue.
We have populated all four caps (C304, C305, C306, and C307). You are right about this configuration, we are shorting output 3 and Output 5 of the Clock Generation IC, we used this source link.
https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
Given the desired signal at 1 MHz (50% duty cycle PWM signal), we knew that 1 MHz is relatively low in comparison to 50 MHz, but when we applied that 1 MHz analog sinusoidal input to the ad9467, the analog input bandpass filter was fine.
Here is the picture:
- Results that are required to be displayed on the ADI IIO Oscilloscope are obtained at the clock frequency of 170-180 Mhz displayed on the Vitis Serial Terminal.
However, when we provided an analog signal other than sinusoidal input, the bandpass filter at the input side distorted our entire signal. As a result, the bandpass filter eliminated the majority of our signal's components.
Here is the snapshot:
- Results that are required to be displayed on the ADI IIO Oscilloscope are obtained at the clock frequency of 170-180 Mhz displayed on the Vitis Serial Terminal.
Therefore, please provide the input filter configuration that how the resistors and capacitors will be utilized to retain the voltage waveform (square, triangular, etc) at 1Mhz and 50% duty cycle.
Thanks
Abbas Ali
FPGA Engineer
