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AD9083 Recommended for New Designs
The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time S-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter...
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AD9083 on Analog.com

jesd204b configuration for AD9083

Shun21

on Mar 12, 2023

Category: Software

Product Number: AD9083

Software Version: Vivado2019.2

Hi,ADI

If my jesd204b has L=1,then the ad9083 will transmit through that line?

And how do I confirm that the JESD204B configuration is complete after the jesd204b configuration is done?
I hope someone will have some free time to reply to me.

Best regards,
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0 Brigid.Duggan

on Mar 20, 2023 8:01 AM
Hi, you could write a short script to check the status of the JTX_PHASE _ESTABLISHED bit ...in register 0x313, in the API script when you have no errors returned then the link is good

0x313

PHASE_ESTABLISH_
STATUS

[7:1]

RESERVED

Reserved.

0x0

R

0

JTX_PHASE_ESTABLISHED

phase established readback.

0x0

R
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0 Brigid.Duggan

on Mar 20, 2023 1:44 PM
Hi ,

In addition to below, in order to check that the link has been established.... For that, you need to check status bits in the FPGA. You should have bits akin to “CGS complete”, “Frame Sync established”, “ILA complete”, and “Data_ready”. you can check the documentation for the IP you are using for the names of these status bits.

regards Brigid.
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