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ad9681 test pattern output

Category: Hardware
Product Number: ad9681

Hello,

I am confused with the ad9681 test pattern output. I am working in test pattern mode. The data I read from 4 adcs from the same bank must be the same, right? However, I'm getting data different by 1 one clock in the same bank. I applied xapp1017. where could the problem be?

I also applied digital reset.(register 0x08 -> 3)


thanks

  • Hi akgulb,

    Thanks for your interest in AD9681.

    Kindly elaborate what type of test pattern did you use. It would be also helpful for us if you can provide the data pattern results of 4 ADCs, and the register configuration sequence that you've made. Did you use an evaluation board for this?

    Thank you and regards,

    Xavier

  • Hi jxav,

    I'm using our custom board which has artix-7 fpga (xc7a200t) and 2xAD9681.  Firstly, I'm appliyng digital reset. after that I do sync sequence. The register order as follows:

    0x08 -> 3

    0x08 -> 0

    0x109 -> 2 (sync next only) 

    Then I'm sending SYNC signal.

    I'm using checkerboard and pn9 sequence test patterns. the results are as follows;

    (for checcker board)

    b1_adc1 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 - ...

    b1_adc2 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 - ...

    b1_adc3 -> 5554 - aaa8 - 5554 - aaa8 - 5554 - aaa8...

    b1_adc4 -> 5554 - aaa8 - 5554 - aaa8 - 5554 - aaa8 ...

    b2_adc1 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 - ...

    b2_adc2 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 - ...

    b2_adc3 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 - ...

    b2_adc4 -> aaa8 - 5554 - aaa8 - 5554 - aaa8 - 5554 -  ...

    (for pn9)

    b1_adc1-> 6e00- 4e8c-75d0-9218-f0bc

    b1_adc2-> 6e00- 4e8c-75d0-9218-f0bc

    b1_adc3-> 4e8c-75d0-9218-f0bc- ecd0

    b1_adc4-> 4e8c-75d0-9218-f0bc- ecd0

    b2_adc1-> 9184-b954-06f0-b720-2154

    b2_adc2-> 9184-b954-06f0-b720-2154

    b2_adc3-> b954-06f0-b720-2154-1fac

    b2_adc4-> b954-06f0-b720-2154-1fac

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