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AD9689: Multichip NCO Synchronization

Category: Datasheet/Specs
Product Number: AD9689

Hello,

I will revise the text and ask the question again.

I have a question from our customer about "NCO Multichip Synchronization" of AD9689.

The "NCO Multichip Synchronization" section, page-53 to 54 of the datasheet(Rev.A), unmentioned the setting of register 0x0300 "DDC Sync Control".

After setting 0x0040, 0x0041, and 0x0042, the MNTO signal will be triggered by the SYSREF signal after setting 0x0120[2:1]=11b. (Figure 117)
Figure 117 indicates that the LMFC and NCO are synchronized at the MNTO de-asserted.
But the datasheet unmentioned the settings of 0x0300 "DDC Sync Control" in MNTO/SNTI synchronization.

I understand that the setting of 0x0300[2:1] will be needed in SYSREF continuous mode or N-Shot mode.
Is it not necessary to set 0x0300[2:1]=11b in MNTO/SNTI synchronization?

Best regards,

y_suzuki



asking again
[edited by: y_suzuki at 5:36 AM (GMT -4) on 5 Jul 2023]