I have a question about "NCO Multichip Synchronization" of AD9689.
In the "NCO Multichip Synchronization" section, page-53 to 54 of the datasheet(Rev.A), it includes NCO synchronization but It unmentioned the setting of register 0x0300 "DDC Sync Control".
After settings of 0x0040, 0x0041, and 0x0042, the MNTO signal is triggered by SYSREF signal after writing 0x0120[2:1]=11b and deassert the MNTO by the next SYSREF. (Figure 117)
Figure 117 is indicating that the LMFC and NCO are synchronized at the MNTO deassert. But they unmentioned 0x0300 "DDC Sync Control".
Doesn't it need the settings of 0x0300[1:0]=11b before configuring 0x0120[2:1]=11b to synchronize NCO?