My goal is to use a single FPGA board (Xilinx ZCU102) to receive the data from four AD9695 chips on our custom pcb board. Since there would be 4 links of data from 4 ADC chips, we need to make sure that the datas are synchronized at the end of JESD204B receiver.
I've read some technical articles that ADI provides (ref1, ref2, ref3) and AD9695 datasheet. So far, I understand that:
1. AD9695 supports either subclass 0 or 1 to do synchronization of multiple chips.
2. Subclass 0 doesn't provide deterministic latency. It utilizes "timestamp mode" by applying SYSREF on JESD Tx to set the control bit as timestamps. At JESD Rx, it aligns these timestamps to synchronize the data from different links.
3. Subclass 1 provides deterministic latency (DL). It utilizes "normal mode" by applying SYSREF as a global reference on both JESD Tx & Rx to align the local multiframe clocks (LMFC) from multiple links. At JESD Rx, the receiver buffers use these "SYSREF aligned" LMFCs to release the data from different links at the same time to achieve DL every power cycle and synchronize the data from different links.
Please point out if there's any misunderstanding above.
My question is, if our system doesn't have any specific requirement for deterministic latency (i.e. we don't need this latency as feeback calibretion reference), do you recommend us use sub 0 or 1?
I believe sub 0 maybe easier to implement, but would there be any shortcoming if we use it to synchronize our system?
Thank you so much!!